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    Inheritance in HDL languages

    Hello,

    I am wondering if there is any form of inheritance in VHDL or Verilog. I am not very expierienced user of these languages, but several times in my projects (VHDL mostly) I noticed that inheritance would simplify them. I mean inheritance as it is defined in object oriented languages like Java or C++. The ability to extend existing in project entities/modules can save many time during development.

    If such option exists, for what languages and tools for synthesis (FPGA).

    Regards

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    Re: Inheritance in HDL languages

    System verilog supports classes and inheritance, but none of it is supported for synthesis and used for simulation only

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    What features are you trying to use, as inheritance is not something I've ever considered useful for hdl. Re usable code can be put into packages.



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    Re: Inheritance in HDL languages

    Hello,

    thanks for quick answer. I have module (Verilog) with soft-processor (Briey SoC - RISC-V). This module requires two clocks - one for AXI bus and second for VGA. I would add two PLLs clocks and extend existing module - make it new top module (all signals in old module minus these two clock signals). There are many I/O and buses lines, so inheritance can save a lot of time, creating new module.

    Regards



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    Re: Inheritance in HDL languages

    Quote Originally Posted by TrickyDicky View Post
    System verilog supports classes and inheritance, but none of it is supported for synthesis and used for simulation only
    I could see it being supported for class functions on abstract classes. This, along with "let", is how SV emulates VHDL-style unconstrained vector functions. I could see this being supported for synthesis in this very specific case.



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    Re: Inheritance in HDL languages

    Possibly, but given the speed of language feature support in some tools don't expect it anytime soon



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    Re: Inheritance in HDL languages

    Hello,

    I realized that SpinalHDL has full inheritance because it is based on Scala programming language. Drawback is that SpinalHDL is not direct tool for syntessis of FPGA, it just generate Verilog source files. I dont know it (SpinalHDL), so the investment to learn it myself is unproifitable for me ;)

    Regards
    Last edited by FlyingDutch; 15th April 2019 at 18:47.



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    Re: Inheritance in HDL languages

    If you're of the python persuasion, there is also myHDL. It also generates vhdl or verilog for synthesis but it gives you access to python for testing.


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    Re: Inheritance in HDL languages

    also, it is possible to use generics/parameters to extend modules at synthesis time. This isn't as clean for port maps, but Verilog does allow you to have unconnected "open" ports. You can create wrapper files to clean up the port/params. VHDL also allows this as long as the port is not an "unconstrained" type. People have also made code-generators for Verilog/VHDL projects.


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