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Did you try to adjust the input offset to get midscale output in open loop?
So you close the loop.How is that ever possible ? provided that the opamp has large gain
In open-loop, the output will be at either high or low voltage rail
The input is biased at ground instead of 1/2 the supply voltage.Oh, the circuit has so little gain-bandwidth product. Why ?
How did you arrive at the compensation capacitor values? The seem quite big related to the small transistors.the circuit has so little gain-bandwidth product. Why ?
The input common mode range probably includes the negative rail, but the shown bias also forces the OP output to V-. Can't expect any performance this way. Think again!The input is biased at ground instead of 1/2 the supply voltage.
You can do a dc sweep of the input voltage from 0V to the supply voltage with a gain of 1 configuration and observe the output.I will test input common mode range later. Do you have a recommended test circuit for input common mode range ?
There is something I don't quite understand in this circuit. C1 is connected around a non-inverting stage and thus provides positive feedback so the effective capacitance at the output of the 1st stage looking into the input of the 2nd stage is negative. Unless the idea is to cancel positive capacitance with this negative capacitance but this is not going to work well because of all sorts of variations. Plus, one needs big positive cap there to create the dominant pole and stabilize the loop. Or maybe this is meant to be a feed-forward capacitance. Looks to me that the 2nd stage has gain bigger than 1 and in this case C1 will feedback current to the 1st stage rather than feed forward. In any case it is two directional path.
What would happen with the loop stability if C1 is disconnected? Or maybe reduce C1 value with respect to C2, because C2 is the one providing the Miller compensation.