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    Opamp circuit simulation

    Is the following open loop transient simulation of opamp correct ?


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    Re: Opamp circuit simulation

    Ok, I understood why the output is pulled to the high voltage side.

    The culprit is M11. Vgd of M11 is 1.2V-0.25V ~= 1V. How to make M11 to be in saturation region ?

    - - - Updated - - -

    I have updated my opamp circuit with negative feedback and the output voltage is now less than 2.5V

    And all mosfets are in saturation.

    Please correct me if wrong




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    Re: Opamp circuit simulation

    The post #1 circuit output is at the positive rail because you apply a positive input offset voltage and don't use any means to achieve a correct DC bias. Did you try to adjust the input offset to get midscale output in open loop?

    Generally open loop analysis without appropriate DC bias is a bad idea.



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    Re: Opamp circuit simulation

    Did you try to adjust the input offset to get midscale output in open loop?
    How is that ever possible ? provided that the opamp has large gain

    In open-loop, the output will be at either high or low voltage rail



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    Re: Opamp circuit simulation

    I don't understand the biasing of your current sources. M10 has a drain current source of 10\mu A. But instead of connecting it in a diode fashion, you connected a voltage source to the gate.

    Also M13, M12, M11 and M15 is a sort of common source stage (a cascade of a common source stage with a diode load and a common source stage). And then you use it as the input to your third stage (M14 and M16) which also has a PMOS driven by what was also input to your M13. Its like a push-pull pair but why have the stage consisting of M13, M12, M11 and M15?


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    Re: Opamp circuit simulation

    See http://asco.sourceforge.net/doc/ASCO.pdf#page=40

    Most likely M10 connection is wrong. Let me check



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    Re: Opamp circuit simulation

    Quote Originally Posted by promach View Post
    How is that ever possible ? provided that the opamp has large gain

    In open-loop, the output will be at either high or low voltage rail
    So you close the loop.
    You can apply DC negative feedback from the output to the (-) input with a very low frequency RC low-pass filter in the loop (such as 10k ohm resistor in series with a 10 Farad cap to ground at the input.)
    That will stabilize the DC bias without affecting the open-loop AC gain down to a very low frequency.
    Zapper
    Curmudgeon Elektroniker


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    Re: Opamp circuit simulation

    Oh, the circuit has so little gain-bandwidth product. Why ?




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    Re: Opamp circuit simulation

    Quote Originally Posted by promach View Post
    Oh, the circuit has so little gain-bandwidth product. Why ?
    The input is biased at ground instead of 1/2 the supply voltage.
    Zapper
    Curmudgeon Elektroniker



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    Re: Opamp circuit simulation

    the circuit has so little gain-bandwidth product. Why ?
    How did you arrive at the compensation capacitor values? The seem quite big related to the small transistors.

    - - - Updated - - -

    The input is biased at ground instead of 1/2 the supply voltage.
    The input common mode range probably includes the negative rail, but the shown bias also forces the OP output to V-. Can't expect any performance this way. Think again!


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    Re: Opamp circuit simulation

    See this updated circuit. Any comments ?

    I will test input common mode range later. Do you have a recommended test circuit for input common mode range ?




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    Re: Opamp circuit simulation

    Quote Originally Posted by promach View Post
    I will test input common mode range later. Do you have a recommended test circuit for input common mode range ?
    You can do a dc sweep of the input voltage from 0V to the supply voltage with a gain of 1 configuration and observe the output.
    Zapper
    Curmudgeon Elektroniker



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    Re: Opamp circuit simulation

    There is something I don't quite understand in this circuit. C1 is connected around a non-inverting stage and thus provides positive feedback so the effective capacitance at the output of the 1st stage looking into the input of the 2nd stage is negative. Unless the idea is to cancel positive capacitance with this negative capacitance but this is not going to work well because of all sorts of variations. Plus, one needs big positive cap there to create the dominant pole and stabilize the loop. Or maybe this is meant to be a feed-forward capacitance. Looks to me that the 2nd stage has gain bigger than 1 and in this case C1 will feedback current to the 1st stage rather than feed forward. In any case it is two directional path.
    What would happen with the loop stability if C1 is disconnected? Or maybe reduce C1 value with respect to C2, because C2 is the one providing the Miller compensation.
    Last edited by sutapanaki; 14th April 2019 at 22:14.



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    Re: Opamp circuit simulation

    Quote Originally Posted by sutapanaki View Post
    There is something I don't quite understand in this circuit. C1 is connected around a non-inverting stage and thus provides positive feedback so the effective capacitance at the output of the 1st stage looking into the input of the 2nd stage is negative. Unless the idea is to cancel positive capacitance with this negative capacitance but this is not going to work well because of all sorts of variations. Plus, one needs big positive cap there to create the dominant pole and stabilize the loop. Or maybe this is meant to be a feed-forward capacitance. Looks to me that the 2nd stage has gain bigger than 1 and in this case C1 will feedback current to the 1st stage rather than feed forward. In any case it is two directional path.
    What would happen with the loop stability if C1 is disconnected? Or maybe reduce C1 value with respect to C2, because C2 is the one providing the Miller compensation.
    You can refer to the following paper that describes this circuit in details: "Positive Feedback Frequency Compensation for Low-Voltage Low-Power Three-Stage Amplifier" from Steyaert's group at KU Leuven.



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    Re: Opamp circuit simulation

    What do you guys think about the circuit at the left side ?

    Someone helped me to improve the cascade mirror stack, but it degrades the phase margin though.

    Could anyone explain analytically on cascn, cascp and biascn ?

    Last edited by promach; 15th April 2019 at 02:27.



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    Re: Opamp circuit simulation

    For improving phase margin of opamp3.asc , I use an extra series resistor to put a zero near the unity gain frequency.
    but then, good accurate resistor is hard to fabricate.

    So, let me ask: anyone have any idea on how to replace both the ideal current source and the extra resistor with a mosfet in ohmic region without using any extra bias voltage source ?

    In other words, is it possible to use constant gm bias circuit in both opamp3.asc and opamp.asc circuit ?

    Last edited by promach; 15th April 2019 at 15:59.



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    Re: Opamp circuit simulation

    I managed to get unity-gain bandwidth = 275MHz , phase margin = 76 degrees , Gain = 93 dB , Power dissipation = 366 uW

    Last edited by promach; Today at 07:10.



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    Re: Opamp circuit simulation

    Can you do a step response? It is interesting to see how it settles to a pulse.



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    Re: Opamp circuit simulation

    See https://github.com/promach/opamp

    Could you propose a suitable testing circuit configuration for settling time ?



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    Re: Opamp circuit simulation

    Decide about the amplifier configuration (e.g. noninverting buffer), input voltage range (e.g. 0.5..1.5V), settling performance (e.g. to 0.1 % of final value). Apply the input signal, plot V(out)-V(In+). Sketch error band and determine when the output stays within.

    Click image for larger version. 

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