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12th April 2019, 14:18 #1
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Design to state position of first one from lsb every clock for parallel data coming
Can you please provide a design whose output will state the location of the first '1' from the LSB for an incoming parallel bit stream every clock?

12th April 2019, 14:34 #2
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Re: Design to state position of first one from lsb every clock for parallel data comi
Is this a homework?
Really, I am not Sam.

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12th April 2019, 14:36 #3
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12th April 2019, 16:16 #4
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Re: Design to state position of first one from lsb every clock for parallel data comi
You seem to have a misconception of what this forum is about. Members will help you with answering questions you may have on a variety of electronics related topics. They will assist you in resolving problems you may have in code or concepts. What members are unlikely to help with is: Doing your work for you.
You have an assignment or a need to have this circuit then do one or more of the following:
a) design it yourself
b) hire someone to design it, if you are not capable of designing such a circuit
c) try to design it and ask questions on the forum (showing what you have done) about any problems with your circuit that you can't figure out how to fix.
d) search the internet for your answer
Of the various options you will learn the most by doing either a or c.

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12th April 2019, 22:18 #5
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14th April 2019, 08:44 #6
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Re: Design to state position of first one from lsb every clock for parallel data comi
There are 23 ways to code this. The obvious is a for loop from msb to lsb. This actually works when the synthesis tool understands and implements this in a good way. The fancy way uses "bitscan" with (x) & (x). This expression returns a onehot vector with the lowest 1 being the only bit set. The third method is manually generating the logic for a priority encoder.
There is also a priority encoder implementation that takes a 1hot vector and does the andor mapreduce with 10101010, 11001100, 11110000, etc...

14th April 2019, 11:49 #7
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Re: Design to state position of first one from lsb every clock for parallel data comi

14th April 2019, 12:16 #8
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Re: Design to state position of first one from lsb every clock for parallel data comi
What is x and what is x?
In my view, a behavioral description of the intended logic, typically using a for loop is a straightforward approach to synthesize it, as long as you don't have additional requirements, e.g. implementing pipelining or enforcing a specific hardware implementation like using carry chains to speed up the design.
Some synthesis tools have difficulties to implement nonarithmetic problems like priority encoder optimally following a behavioral description, but they are always able to implement it correctly.

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15th April 2019, 18:53 #9
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Re: Design to state position of first one from lsb every clock for parallel data comi
Code:for (i=0; i<WIDTH, i=i+1) begin if (input[i]) begin position = i; break; end end
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