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    Link Training with IO DELAY

    Hi,
    how to implement link training with IO DELAY in Xilinx ultrascale FPGA?
    Any idea or reference design?
    Thanks

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    Re: Link Training with IO DELAY

    In essence - "link training" is the process of finding the safest sampling point at receiver to avoid timings violations and achieve a robust link.
    In the Ultrascale family the recommendation is to use the "bitslice" component.

    Google XAPP1274


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    Re: Link Training with IO DELAY

    @shaiko, is this training also with IO DELAY? I see in page 315
    https://www.xilinx.com/support/docum...-libraries.pdf
    IDELAYE3 primitive.



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    Re: Link Training with IO DELAY

    Yes.
    The "bitslice" is an IOSERDES, IODELAY and FIFO aggregated into one primitive.
    Before Ultrascale - series 7 had these separately.

    The new approach is what Xilinx calls: "Native Mode".
    The old approach (Series 7) is called: "Component Mode".
    You can still use "Component Mode" with Ultrascale - however, it's inadvisable unless you have a good reason to do so...

    https://www.youtube.com/watch?v=ihk7YbZqCKA

    Enjoy


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    Re: Link Training with IO DELAY

    @shaiko
    This solution seems like source synchronous. Is there one which is not source synchronous and also support smaller FPGA like artix?



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    Re: Link Training with IO DELAY

    What is your communication protocol ?



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    Re: Link Training with IO DELAY

    There is no specific protocol. I have just 4 I/O pins on TX end and 4 I/O pins on RX end and using 2 in one direction and remaining 2 on another direction at each end. At the moment I send some known pattern from each end and verify on another end and then send the data and it works at 100 MHz.



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    Re: Link Training with IO DELAY

    At 100MHz - why do you want to use a SERDES ?
    Why not implement a simple synchronous interface (like SPI) ?



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