blindscience
Newbie level 4
I have parameterized Verilog that works in Quartus and Modelsim, but I'm having trouble getting it to work in Design Compiler. Basically, the issue is that if I instantiate a module with parameter other than the default value, I get the problem:
Information: Building the design 'child' instantiated from design 'parent' with
the parameters "WIDTH=NON_DEFAULT_PARAMETER_VALUE". (HDL-193)
Warning: Cannot find the design 'child' in the library 'WORK'. (LBR-1)
I found a post outlining the exact same problem from 2016, but the solution was unclear.
I've tried both Verilog 2001 syntax:
And Verilog 95 syntax:
Information: Building the design 'child' instantiated from design 'parent' with
the parameters "WIDTH=NON_DEFAULT_PARAMETER_VALUE". (HDL-193)
Warning: Cannot find the design 'child' in the library 'WORK'. (LBR-1)
I found a post outlining the exact same problem from 2016, but the solution was unclear.
I've tried both Verilog 2001 syntax:
Code:
module child
#(
parameter WIDTH = 1
)
(
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
assign out = in;
endmodule
module parent
logic [63:0] tempIn;
logic [63:0] tempOut;
child #( .WIDTH(64) ) childInst <== instantiating with WIDTH=1 works
(
.in(tempIn),
.out(tempOut)
);
endmoduleAnd Verilog 95 syntax:
Code:
module child
(in, out);
parameter WIDTH = 1;
input wire [WIDTH-1:0] in;
output wire [WIDTH-1:0] out;
assign out = in;
endmodule
module parent
logic [63:0] tempIn;
logic [63:0] tempOut;
defparam childInst.WIDTH = 64; <== Setting to WIDTH=1 works
child childInst
(
.in(tempIn),
.out(tempOut)
);
endmodule