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Sigma Delta output not constant

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Hi, I have a discrete time sigma delta. I apply a DC input 100mV away from midscale. The output code (after filter and decimator) is not stable, it changes by a few codes each output. OSR is 364. It looks like noise but results of a tran sim without any tran noise applied. Any ideas what causes this? DC gain of integrators is >80dB, outputs of integrators not saturating. Settling time of switches look OK. Could it be switch charge injection? Thanks.
 

Or could it be just instability of the sigma-delta loop?
 

I'd bet that the 'scope says your 100mV with respect
to ADC input reference carries millivolts of noise. If you
can resolve that, even. How many codes (LSBs) would
that be?

You might experiment with things like bond-wire shorting
the ADC input to the ADC reference (or some on-chip
known-not-noisy signal source) and see what comes
out the back when nothing even touches the outside
world.

Because the outside world is grimy and lumpy.

This is why much ADC ATE testing has come to be done
by large sample statistics, the mean or median is the
best you can do. A one-shot test will almost never give
you the same answer, twice. And there goes your drift,
for reliability testing.
 

I read post #1 so that you are reporting simulation results rather than real measurements. Most SD modulators have some kind of pseudo random idle noise respectively limit cycles with constant input, it's just normal operation. The noise pattern can be already found in a numerical analysis of the ideal modulator, although it's probably modified by real circuit properties.

The effects are described in basic SD literature.
 

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