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    HDMI in and out , just connected in to out.

    Hello Dears

    Signal coming from raspberry and i check this by divide clk and send to leds. and also can output to monitor hdmi in use Mike Fiels projects.

    But smth strange and i cannot deliver signal from raspberry to monitor make just pipe from FPGA Virtex4.


    Code:
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    use ieee.numeric_std.all;
    
    library UNISIM;
    use UNISIM.VComponents.all;
    
    entity hdmi_design is
        Port ( led           : inout   std_logic_vector(3 downto 0) :=(others => '0');
    	         
    			  debug         : out    std_logic;
    	 
    			  btn           : in    std_logic;
    			  hdmi_rx_n     : in    std_logic_vector(3 downto 0);
    			  hdmi_rx_p     : in    std_logic_vector(3 downto 0);
    			  hdmi_tx_p     : out   std_logic_vector(3 downto 0);
    			  hdmi_tx_n     : out   std_logic_vector(3 downto 0));
    end hdmi_design;
    
    architecture Behavioral of hdmi_design is
    
        signal hdmi_clk ,reset : std_logic;
        signal tmds_in ,tmds_out  : std_logic_vector(3 downto 0);
    	 
    begin
    
    process (hdmi_clk,reset) -- blinker
    	variable count: integer range 0 to 48000000 := 0;
    begin
    if 	(reset = '0') then
    		count := 0; led <= "0000";
    elsif (hdmi_clk'event and hdmi_clk = '1') then -- 
    	count := count + 1;
    	if		(count = 48000000) then
    		led(0) <= not led(0); count := 0;
    	elsif (count = 36000000) then
    		led(1) <= not led(1);
    	elsif (count = 24000000) then
    		led(2) <= not led(2);
    	elsif (count = 12000000) then
    		led(3) <= not led(3);
    	end if;
    end if;
    end process;
        debug <= tmds_in(3);
       tmds_out <= tmds_in;
    	hdmi_clk <= tmds_in(3);
    
    	in_clk_buf: IBUFDS generic map ( IOSTANDARD => "LVDSEXT_25")
     port map ( I  => hdmi_rx_p(3),  IB => hdmi_rx_n(3),  O  => tmds_in(3));
     
    in_rx0_buf: IBUFDS generic map ( IOSTANDARD => "LVDSEXT_25")
     port map ( I  => hdmi_rx_p(0),  IB => hdmi_rx_n(0),  O  => tmds_in(0));
    
    in_rx1_buf: IBUFDS generic map ( IOSTANDARD => "LVDSEXT_25")
     port map ( I  => hdmi_rx_p(1),  IB => hdmi_rx_n(1),  O  => tmds_in(1));
    
    in_rx2_buf: IBUFDS generic map ( IOSTANDARD => "LVDSEXT_25")
     port map ( I  => hdmi_rx_p(2),  IB => hdmi_rx_n(2),  O  => tmds_in(2));
    
    
    
    out_clk_buf: OBUFDS generic map ( IOSTANDARD => "LVDSEXT_25",  SLEW => "FAST")
        port map ( O  => hdmi_tx_p(3), OB => hdmi_tx_n(3), I => tmds_out(3));
        
    out_tx0_buf: OBUFDS generic map ( IOSTANDARD => "LVDSEXT_25",  SLEW => "FAST")
        port map ( O  => hdmi_tx_p(0), OB => hdmi_tx_n(0), I  => tmds_out(0));
    
    out_tx1_buf: OBUFDS generic map ( IOSTANDARD => "LVDSEXT_25",  SLEW => "FAST")
        port map ( O  => hdmi_tx_p(1), OB => hdmi_tx_n(1), I  => tmds_out(1));
    
    out_tx2_buf: OBUFDS generic map ( IOSTANDARD => "LVDSEXT_25",  SLEW => "FAST")
        port map ( O  => hdmi_tx_p(2), OB => hdmi_tx_n(2), I  => tmds_out(2));
    
    IBUF_inst_puW : IBUF			-- pushW
       port map (  O => reset,      I => btn      );
        
    end Behavioral;
    Code:
    NET hdmi_rx_p<3>      LOC = C33 | IOSTANDARD= LVDSEXT_25  | CLOCK_DEDICATED_ROUTE = FALSE;   #pos J4.74_C33 (IO_L7P_9) 
    NET hdmi_rx_n<3>      LOC = C34 | IOSTANDARD= LVDSEXT_25  | CLOCK_DEDICATED_ROUTE = FALSE;   #neg J4.71_C34 (IO_L7N_9) 
    NET hdmi_rx_p<2>      LOC = F33 | IOSTANDARD= LVDSEXT_25  | CLOCK_DEDICATED_ROUTE = FALSE;   #pos J4.77_F33 (IO_L14P_9) 
    NET hdmi_rx_n<2>      LOC = F34 | IOSTANDARD= LVDSEXT_25  | CLOCK_DEDICATED_ROUTE = FALSE;   #neg J4.80_F34 (IO_L14N_9) 
    NET hdmi_rx_p<1>      LOC = H33 | IOSTANDARD= LVDSEXT_25  | CLOCK_DEDICATED_ROUTE = FALSE;   #pos J4.79_H33 (IO_L22P_9)
    NET hdmi_rx_n<1>      LOC = H34 | IOSTANDARD= LVDSEXT_25  | CLOCK_DEDICATED_ROUTE = FALSE;   #neg J4.82_H34 (IO_L22N_9) 
    NET hdmi_rx_p<0>      LOC = J34 | IOSTANDARD= LVDSEXT_25  | CLOCK_DEDICATED_ROUTE = FALSE;   #pos J4.83_J34 (IO_L29P_9) 
    NET hdmi_rx_n<0>      LOC = K34 | IOSTANDARD= LVDSEXT_25  | CLOCK_DEDICATED_ROUTE = FALSE;   #neg J4.86_K34 (IO_L29N_9) 
    
    NET "hdmi_tx_n<3>"LOC = "A21" | IOSTANDARD = LVDSEXT_25;#   | #neg J4.49_A21 (IO_L21N_5)
    NET "hdmi_tx_p<3>"LOC = "B21" | IOSTANDARD = LVDSEXT_25;#   | #pos J4.52_B21 (IO_L21P_5)
    NET "hdmi_tx_n<2>"LOC = "B26" | IOSTANDARD = LVDSEXT_25;#   | #neg J4.55_B26 ----------------- CLOCK NEGATIVE
    NET "hdmi_tx_p<2>"LOC = "A26" | IOSTANDARD = LVDSEXT_25;#   | 58    ----------------- CLOCK POZITIVE
    NET "hdmi_tx_n<1>"LOC = "B30" | IOSTANDARD = LVDSEXT_25;#   | #neg J4.61_B30(IO_L18N_5
    NET "hdmi_tx_p<1>"LOC = "A30" | IOSTANDARD = LVDSEXT_25;#   | #pos J4.64_A30(IO_L18P
    NET "hdmi_tx_p<0>"LOC = "B32" | IOSTANDARD = LVDSEXT_25;#   | #pos J4.67_B32(IO_L31P_5)    
    NET "hdmi_tx_n<0>"LOC = "B33" | IOSTANDARD = LVDSEXT_25;#   | #neg J4.70_B33(IO_L31N_5)
    
    net   btn   loc = H30     | PULLUP;
    
    net led<0> loc = K33 ;
    net led<1> loc = L34 ;
    net led<2> loc = L33 ;
    net led<3> loc = M33 ;
    
    #net	J4_J5<164> loc = 	AF33	 |  IOSTANDARD = LVCMOS33 | PULLDOWN;	#	J5.84_AF33
    #net	J4_J5<165> loc = 	AE33	 |  IOSTANDARD = LVCMOS33 | PULLDOWN;	#	J5.85_AE33
    #net	J4_J5<166> loc = 	AC34	 |  IOSTANDARD = LVCMOS33 | PULLDOWN;	#	J5.86_AC34
    net	debug loc = 	AD34	 |  IOSTANDARD = LVCMOS33 | PULLDOWN;	#	J5.87_AD34
    I found this link by other issue but very same , but cannot use fpga_editor : https://forums.xilinx.com/t5/7-Serie...-2/td-p/418307 how to check this ?

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  2. #2
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    Re: HDMI in and out , just connected in to out.

    How do you get the hdmi_clk signal?
    I don't see the hdmi_clk signal in the top level ports and neither the reset!
    Why is the led port signal of inout nature, you just want to drive them right?

    From your description, I also didn't understand what you are trying to achieve.
    FPGA enthusiast!



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    Re: HDMI in and out , just connected in to out.

    Quote Originally Posted by dpaul View Post
    How do you get the hdmi_clk signal?
    I don't see the hdmi_clk signal in the top level ports and neither the reset!
    Why is the led port signal of inout nature, you just want to drive them right?

    From your description, I also didn't understand what you are trying to achieve.
    the hdmi_clk signal is tapped off of the hdmi_rx_p/n(3) signal. They are then using the hdmi_clk signal to clock the led output along with passing all the hdmi_rx_p/n to hdmi_tx_p/n pins.

    I also don't understand what the problem is, though given what they have shown I don't know if they are taking in account that the rx to tx inputs to outputs will be skewed and that this may cause problems.

    - - - Updated - - -

    I also noticed they used led : inout instead of led : out probably because they don't understand that pre 2005? that you can't read an out port within an architecture. As they are using an inout port but don't have a tri-state control and it looks like they are routing a non-clock input pin to a clock they have some architectural problems in their code, which is resulting in that unroutable design error (Route Error (471) ISE 14.2)

    FYI next time put the error in your first post don't make people go to another link to figure out what your error is.



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    Re: HDMI in and out , just connected in to out.

    I have generated diff signal from a board and connect to diff input and it works well, so that mean i cannot get signal, and electrical parameters are wrong even i connect GND and 5+ to HDMI. tried DIFF_TERM = FALSE|TRUE, LVDS_25, ULVDS_25, LVDSEXT_25, documentation Virtex4 libarary guide and etc . No result , SOS Help!!



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    Re: HDMI in and out , just connected in to out.

    Are there problems with lower resolutions?



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    Re: HDMI in and out , just connected in to out.

    code can receive only 720p,i did not understand code fully so cannot change to 480p or others. this is hamstwerworks projects in HDMI.



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    Re: HDMI in and out , just connected in to out.

    I mean it for other more code where is it use ISERDES OSERDES and etc.. I found verilog code for 480p but it works but not generate 480p it generate 1024-600 pixels.



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  8. #8
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    Re: HDMI in and out , just connected in to out.

    But smth strange and i cannot deliver signal from raspberry to monitor make just pipe from FPGA Virtex4.
    I have to understand what you are exactly doing.

    Is it like the following?
    Code:
    Raspberry Pi HDMI o/p --> Virtex 4 --> HDMI out to display
                                |
              *do something here after obtaining a single-ended clk from a diff clk*
    And your problem is, you cannot get an o/p on the final display, while the LEDs on the dev-board are blinking as you expecting them to be?
    FPGA enthusiast!



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    Re: HDMI in and out , just connected in to out.

    Yes exactly, i want to get video from Raspberry PI and use this.

    Raspberry PI ------>(FPGA--Do_smth_inside--FPGA)----->HDMI Display

    before do smth, i need to have got connection to Raspberry PI to FPGA, i already make connection FPGA to DISPLAY, after i got connection to Raspi i will Do smth in FPGA and results will see in HDMI DISPLAY.

    LEDs based on HDMI_CLK just for indicate whether signal coming or not. LEDs indicator works on board with Virtex4 VLX100 PLDKIT but not in Virtex4 VSX35 ML402. I found out that VIRTEX4 cannot use tmds_33 , used only lvds.
    Last edited by abimann; 23rd April 2019 at 15:19.



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    Re: HDMI in and out , just connected in to out.

    it works when i make like this :

    (Virtex4_LVDS_480P--------->(Virtex4_LVDS)----------->(HDMI Display_800x600x60hz)



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    Re: HDMI in and out , just connected in to out.

    I would suggest you to first build a successful HDMI pass through project (rather than HDMI I should be saying 480p signal).

    HDMI data in (source can be anything) --> Virtex4 FPGA --> HDMI display capable monitor
    After than you can play around with the signals which are inside the FPGA fabric.

    btw - What is the dev board containing the v4 FPGA?
    FPGA enthusiast!



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    Re: HDMI in and out , just connected in to out.

    yes, but fpga cannot get data from Raspberry thats problem point when i connect to my laptop it gets death blue screen and restarts :) , Xilinx ML402 and and some board with V4 from pldkit.com



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  13. #13
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    Re: HDMI in and out , just connected in to out.

    yes, but fpga cannot get data from Raspberry thats problem point when i connect to my laptop it gets death blue screen and restarts :)
    Now that is a separate problem!
    You need to find out yourself to get an HDMI source before proceeding.
    FPGA enthusiast!



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    Re: HDMI in and out , just connected in to out.

    Click image for larger version. 

Name:	IMG_1381.jpg 
Views:	6 
Size:	498.6 KB 
ID:	152587
    VERY VERY STRANGE
    It is work , but not normally in a picture when i connect Raspi GND and monitor GND without FPGA GND.When i connect FPGA GND monitor doesnot show a picture. why ?
    Thats very strange thing .
    instead of black, there is Green. thats mean no red color ?



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    Re: HDMI in and out , just connected in to out.

    why that's not work? when i connect Raspberry pi HDMI output to FPGA GND ?



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