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    Worst case Corner Analyses in Cadence

    Dear friend, So far I learned from you the setup of Monticarlo, and now I would like to learn how to run the counterpart verification method, the Corner analyses.

    Basically I believe that the worst case corners (WP, WS, WO, WZ) must be covered in MC simulation if we take right number of sampling.


    I am using three instances in my design, MOSFET, Resistors and Capacitors. However when I click on the model file I still see something like Inductive or Bipolar or diodes which I never used in my design, why it is showing up. Do I simply just ignore it and un-tick it ?

    My second problem of making a table covering the all possible corners. As you know MOSFET has (WP, WS, WO, WZ), Resistor has only (WP, WS) and Cap has only (WP, WS).

    is it possible to define a corner where some instances have the WP corner and the other have WS ? or all the instances must have the same corner type.

    Thank you very much in advance

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    Re: Worst case Corner Analyses in Cadence

    Corner simulations are generally more straight forward compared to MC.
    You'll have to give us some more information about your models. Do they take into account the process variations, for example? Usually, foundries supply models that take into account all that. Process corners are usually denoted something like typical, slow, fast, slow-fast, fast-slow. On top of that you may have high and low for resistors. In this case it is just a matter of specifying the correct model file for each process corner. Additionally, you should specify some supply voltage ranges (for example 1.7,1.8,1.9 for 1.8V supply) and some temperature ranges (for ex. 0 50 125).


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    Re: Worst case Corner Analyses in Cadence

    Dear Suta,

    Thank you for your reply

    My MC model file cover the process variation. Also I am simulating the corners under wide range of temperature. But all the simulation I am keeping it with constant voltage supply = 3.3 V.

    Still my problem of choosing the corners that covers all the possibility

    Please see my suggested table of corners below,

    MOSFET Res Cap

    WP WP WP
    WP WS WP
    WP WP WS
    WP WS WS

    WS WP WP
    WS WS WP
    WS WP WS
    WS WS WS

    WO WP WP
    WO WP WS
    WO WS WP
    WO WS WS

    WZ WP WP
    WZ WS WP
    WZ WP WS
    WZ WS WS


    The above table let say digitally cover all the possible variables as a logic, but I don't know if it is right to assume one instance is WP and the other one is different, may be in technology perspective they must all have same condition, by that way the number of corners will be reduced.

    for running the corners I have two options, the first is from ADE by modifying the model file to the selected corner, the other way is from ADX by running the Single Run, Corner Simulation and define my corners there.

    Thank you once again



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    Re: Worst case Corner Analyses in Cadence

    You need to look at the foundry documentation for what are the recommended corners. You should not do all cases possible as some have no physical meaning, some have no realism (will you ever run your chip at military graded temperature extremes like -40C?)
    Really, I am not Sam.


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    Re: Worst case Corner Analyses in Cadence

    The above table let say digitally cover all the possible variables as a logic, but I don't know if it is right to assume one instance is WP and the other one is different, may be in technology perspective they must all have same condition, by that way the number of corners will be reduced.
    No. It is not correct from a technologically point of view. If your corner files are 3 sigma corner files, then each one of them guarantees 99.7% of the samples will be within them. But in a bivariate Gaussian distribution selecting 3sigma corners for two different types of device will make your overall yield (if I remember correctly), 4.5 sigma (if your distributions are independent which is never the case,

    In summary, no it is not technologically correct. But the other alternative is to use Monte Carlo simulation to design which is too time consuming. So designers still stick to 3-sigma corner files unless there is a serious power or area penalty. People also use 2-sigma corners if there are different types of devices.


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    Re: Worst case Corner Analyses in Cadence

    Quote Originally Posted by ThisIsNotSam View Post
    You need to look at the foundry documentation for what are the recommended corners. You should not do all cases possible as some have no physical meaning, some have no realism (will you ever run your chip at military graded temperature extremes like -40C?)
    Dear Thesis

    I am running my simulation under the industrial range of -40 to 85... so -40 is industrial standard most of the commercial chip are tested in this range as I can see from the data sheet, otherwise I will be happy if you tell me I should decrease the range

    - - - Updated - - -

    Quote Originally Posted by vivekroy View Post
    No. It is not correct from a technologically point of view. If your corner files are 3 sigma corner files, then each one of them guarantees 99.7% of the samples will be within them. But in a bivariate Gaussian distribution selecting 3sigma corners for two different types of device will make your overall yield (if I remember correctly), 4.5 sigma (if your distributions are independent which is never the case,

    In summary, no it is not technologically correct. But the other alternative is to use Monte Carlo simulation to design which is too time consuming. So designers still stick to 3-sigma corner files unless there is a serious power or area penalty. People also use 2-sigma corners if there are different types of devices.
    Dear Viver,

    Thank you for your reply

    I am only running corner as a method of confirmation after I already run the MC analyses, I see from your talk that I run the MC then it is waste of time if I simulate the worst case corners and vice versa.

    Please can you suggest me the right table of corners so I will better understand your explanation please



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    Re: Worst case Corner Analyses in Cadence

    I'm not sure you fully understand the purpose of corner simulations. Corners are pre-defined by the foundry. Based on their process they define what parameters of the devices vary which way and by what amount. So, you may have both P and N MOS shifted in the same direction as in slow and fast corners, or you can have them go in opposite ways as in the cross corners slow-fast or fast-slow. In all cases when talking about corners, these are global variations, which means they affex=ct the same way all devices on the chip, wafer, lot, as opposed to local random variations that are captured by MC simulations. The other name for corner simulations is PVT simulation - which suggests that you have to run different combinations of process, voltage (i.e. supply) and temperature.


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    Re: Worst case Corner Analyses in Cadence

    Dear Suta,

    Thank you very much for your explanation.

    I have no doupt of what you kindly presented, only may be you didn't get my question completely or it was a mistake of my explanation. I am working with 0.35 um, the foundry provided me with the technology model file that support both MC and corner analyses. I don't have further information from the foundry about what is possible or not, and therefore I was thinking to cover every possible solution, or to ask if it is general issue.

    Today I have simulated different combination of corner as you said (which led me back to my table), with the industrial temperature range . Only lift with the voltage range,

    Dear Suta, I am also running the MC under tempersture range or it is not neccessary . I mean may be nominal MC might cover every thing no need to define extra corners when working with MC.

    Thank you very much



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    Re: Worst case Corner Analyses in Cadence

    There is that thing called process+mismatch MC that is supposed to cover both the global and local variations in a circuit. I have found that specifically for the technology I work with the variations are less compared to if I run mismatch MC on the worst-case corner (worst case for given parameter of interest).

    You say the foundry provided you with corner models and yet you list in your table things like WS Wp etc, which I'm not quite sure what they mean. Traditionally, the process corners go under the names of slow, fast and so on. This comes from the way devices are being tested for corner allocation. They use ring oscillators and depending on whether the frequency of oscillation is lower or higher than typical the corner is respectively slow or fast.

    In any case, you should have corner names for your models. Different corners are in essence different model files. You don't go and manually change device parameters to get the corner behavior.
    Then it is a matter of just going in ADEXL and creating a setup with different corners for simulation.


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    Re: Worst case Corner Analyses in Cadence

    Dear Suta

    The definition of my technology are describes as :

    WP : worst case power (fast)
    WS : Worst case Speed (Slow)
    WO : Worst case One (Fast NMOS & Slow PMOS)
    WZ : Worst case Zero (Slow NMOS & Fast PMOS)

    I am not at all changing manually any device model parameter nor I am allowed to do, the only thing I choose the corner of interest. Generally I am selecting all possible corner and run the simulation from ADX, kindly you see the picture below. You see I defined the corners on the column C2.

    After running the simulation, the spectra will have 48 corner : Process corner* temperature corners = 16 * 3 = 48

    The number of process corner is taken as in my first post.

    Click image for larger version. 

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    I think now it is becoming clear for you now.

    1. Then you go back please to my question if my table of assumption is correct or not. Let me make it more clear, Can I assume a corner where the Res is fast and the capacitor is slow. Or it should always both fast or slow ??

    2. The second part of my question is about your concept of running the MC around the worst case corner of interest. In my design the Worst case is the WP, do you suggest me to run MC around WP ? In my opinion it is meaning less to perform MC around process corner because the process corner must be already included when performing MC. Unless if you mean not the process corner rather than other parameters like temperature, VDD,..etc

    I do appreciate your continuous help
    Thank you once again



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    Re: Worst case Corner Analyses in Cadence

    Again, you should look for foundry documentation (or ask the right person for it). I can assure you it does exist. Generally speaking, R and C corners are a function of line edge roughness and will shift in the same direction.

    ps: are you using a real PDK or is it some made up kit for training purposes?
    Really, I am not Sam.


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    Re: Worst case Corner Analyses in Cadence

    Dear Thisis

    I am using real PDK from foundry.

    If R and C go only in one direction either both fast or both slow it will be good for my simulation time as it will reduce the number of taken corners, This is what I want to get confirmed



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    Re: Worst case Corner Analyses in Cadence

    OK, now it is clear. I think your ADEXL setup is ok, except that you should also include supply variation. This is important. As to the resistors and capacitors variation, I think the way you defined it in the picture is good. They may go in different direction, not necessarily correlated. Resistors do depend on edge roughness and doping. Capacitors, besides edge roughness will depend also on oxide thickness. In any way it is safer to assume they can go in different directions.

    I don't think it is meaningless to run MC around process corners. Yes, it is true that when you ran MC you should have set up also some process corner, maybe typical. But MC captures only local random variations for a given process. It doesn't capture corner to corner variation which affects all devices in the same way. Unless, of course you run process+mismatch MC as we've already talked about. So, to summarize, Running corners you look for the combination which result in the worst performance because all devices shifted together in certain way. Then you look for the effect of random variations affecting different devices in different ways, which is MC on that worst case corner.


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    Re: Worst case Corner Analyses in Cadence

    Quote Originally Posted by sutapanaki View Post
    As to the resistors and capacitors variation, I think the way you defined it in the picture is good. They may go in different direction, not necessarily correlated. Resistors do depend on edge roughness and doping. Capacitors, besides edge roughness will depend also on oxide thickness. In any way it is safer to assume they can go in different directions.
    Maybe you are talking about gate caps, I was referring to MiM ones.
    Really, I am not Sam.


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    Re: Worst case Corner Analyses in Cadence

    Quote Originally Posted by sutapanaki View Post
    OK, now it is clear. I think your ADEXL setup is ok, except that you should also include supply variation. This is important. As to the resistors and capacitors variation, I think the way you defined it in the picture is good. They may go in different direction, not necessarily correlated. Resistors do depend on edge roughness and doping. Capacitors, besides edge roughness will depend also on oxide thickness. In any way it is safer to assume they can go in different directions.

    I don't think it is meaningless to run MC around process corners. Yes, it is true that when you ran MC you should have set up also some process corner, maybe typical. But MC captures only local random variations for a given process. It doesn't capture corner to corner variation which affects all devices in the same way. Unless, of course you run process+mismatch MC as we've already talked about. So, to summarize, Running corners you look for the combination which result in the worst performance because all devices shifted together in certain way. Then you look for the effect of random variations affecting different devices in different ways, which is MC on that worst case corner.


    Dear Suta,

    Thank you for confirming me the Corner setup.

    I would also summarize what I understood from your last reply,

    1. If I am running MC with only Mismatch then I should run it around my worst corner, which means I have to simulate with Corners like my setup in the image, then I find my worst corner or corners. After that I go to MC and run the Mismatch simulation around this or these corners. In this configuration the Corner simulation find the worst global variation and the MC will introduce the local variation between devices around this corner.

    2. However, and as you thankfully said (''Unless, of course you run process+mismatch''), If I run the MC with (Process and Mismatch) then by this way I already captured the global and random variation so the result should confirm the test, no need to go for corner simulation before MC for this type of MC setup because the global variation is already included with the MC Process.

    3. By either way I should perform my simulation with temperature range as well as with changing supply voltage variation

    Hope I am fully covered your answers correctly



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    Re: Worst case Corner Analyses in Cadence

    Quote Originally Posted by ThisIsNotSam View Post
    Maybe you are talking about gate caps, I was referring to MiM ones.
    The intermetal dielectric in the MiM caps shouldn't be very much correlated with what happens in the resistors. That's my understanding. Then, MiM caps are just one, rather limited option for caps. In 0.35u technology probably they still have poly-poly caps or even the MOM caps have dielectric that's actually the isolation layer between different metal layers, plus the dielectric separating metal wires of the same layer. While the metal spacing for a single layer is pretty well controlled, the dielectric properties are not. All in all, there are too many parameters that affect the value of the caps and I think it is ok to assume that resistors and caps can go in different directions.

    - - - Updated - - -

    Quote Originally Posted by Junus2012 View Post


    3. By either way I should perform my simulation with temperature range as well as with changing supply voltage variation

    Hope I am fully covered your answers correctly
    Yes, mostly correct. Just that running corners you should have one that's the worst amongst all. Or you may have several that show similar worst features. Just pick one of those and then run MC around it. Otherwise it becomes too much for running MC.

    For the process+mismatch MC you may set up the typical corner and then run MC (process+mismatch). And you can repeat for different voltages and temperatures. V and T should not much affect the MC mismatch, though. Also, you should not expect to see same results from process+mismatch MC and mismatch MC run at the worst corner. Usually the latter is worse in terms of variations.


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    Re: Worst case Corner Analyses in Cadence

    Dear Suta,

    May ask you please

    1. Do we need to run the MC or Worst case corner after the layout design as well with the extraction file ?

    2. Does MC or Worst case corner simulations include the geometrical variation by the technology, we know for every technology there is couple on nanometers length that can be tolerated to our design size.

    3. When I run the MC and in the Yield window is giving me the ''Sigma'' and the ''Sigma to Yield'' , I don't understand what these values are telling me. But the general of Sigma you explained for me that was clear

    Thank you in advance



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    Re: Worst case Corner Analyses in Cadence

    Yes, for sure you need to run at least worst case corner on the extracted view. Layout effects and parasitics can change stability, biasing, speed. It is also good to run MC. Results from it could be different from schematic simulation because now you include also layout physical placement effects on matching. So, yes, given the models and the way extraction works, it should include the geometry and placement.
    In my version of cadence I don't have "sigma to yield", I only have min, max, mean and Std Dev (i.e. sigma) and I use that Std Dev to judge about distributions.


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    Re: Worst case Corner Analyses in Cadence

    Thank you Suta for your reply

    For the first part of your answer is becoming clear,

    In the second part it was my mistake about the Sigma to Yield, the true one is "Sigma to target", also "Sigma" and "CDK" as just seen the below image

    Dear Suta, I am also simulating with corner voltage as you suggested. I am working with 3.3 V technology, what is the accepted range for varying the VDD ?

    Click image for larger version. 

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    Thank you very much once again



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    Re: Worst case Corner Analyses in Cadence

    I would say +/-10% around 3.3V should be OK.



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