jylei
Newbie level 1
Hi,
I've been trying to do a layout on the NCSU Design kit provided technology (AMI0.6u).
I am testing a layout on a simple inverter. Everything works great initially, I was able to do DRC, Extracted, and LVS and pass. However, it suddenly won't work today once I want to do a LVS again without me doing any modification. The error message I am getting is attached. Have anyone face similar issue before or know the solution? I've been stuck for 2 days...
Begin netlist: Apr 9 17:40:26 2019
view name list = ("auLvs" "extracted")
stop name list = ("auLvs" "symbol")
library name = "Test"
cell name = "inv"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...
*WARNING* Parameter 'lxUseCell' already exists.
End netlist: Apr 9 17:40:27 2019
Moving original netlist to extNetlist
Removing parasitic components from netlist
presistors removed: 0
pcapacitors removed: 0
pinductors removed: 0
pdiodes removed: 0
trans lines removed: 0
4 nodes merged into 4 nodes
Begin netlist: Apr 9 17:40:27 2019
view name list = ("auLvs" "cmos_sch" "schematic" "symbol")
stop name list = ("auLvs" "symbol")
library name = "Test"
cell name = "inv"
view name = "layout"
globals lib = "basic"
Running Artist Flat Netlisting ...
global error:
Cannot find switch master cell for instance I1 in cellView (inv layout) from viewlist 'auLvs cmos_sch schematic symbol ' in library 'Test'.
global error:
Cannot find switch master cell for instance I2 in cellView (inv layout) from viewlist 'auLvs cmos_sch schematic symbol ' in library 'Test'.
global error:
Cannot find switch master cell for instance I3 in cellView (inv layout) from viewlist 'auLvs cmos_sch schematic symbol ' in library 'Test'.
global error:
Cannot find switch master cell for instance I4 in cellView (inv layout) from viewlist 'auLvs cmos_sch schematic symbol ' in library 'Test'.
si: Netlist did not complete successfully.
End netlist: Apr 9 17:40:27 2019
Comparison program did not complete.
I've been trying to do a layout on the NCSU Design kit provided technology (AMI0.6u).
I am testing a layout on a simple inverter. Everything works great initially, I was able to do DRC, Extracted, and LVS and pass. However, it suddenly won't work today once I want to do a LVS again without me doing any modification. The error message I am getting is attached. Have anyone face similar issue before or know the solution? I've been stuck for 2 days...
Begin netlist: Apr 9 17:40:26 2019
view name list = ("auLvs" "extracted")
stop name list = ("auLvs" "symbol")
library name = "Test"
cell name = "inv"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...
*WARNING* Parameter 'lxUseCell' already exists.
End netlist: Apr 9 17:40:27 2019
Moving original netlist to extNetlist
Removing parasitic components from netlist
presistors removed: 0
pcapacitors removed: 0
pinductors removed: 0
pdiodes removed: 0
trans lines removed: 0
4 nodes merged into 4 nodes
Begin netlist: Apr 9 17:40:27 2019
view name list = ("auLvs" "cmos_sch" "schematic" "symbol")
stop name list = ("auLvs" "symbol")
library name = "Test"
cell name = "inv"
view name = "layout"
globals lib = "basic"
Running Artist Flat Netlisting ...
global error:
Cannot find switch master cell for instance I1 in cellView (inv layout) from viewlist 'auLvs cmos_sch schematic symbol ' in library 'Test'.
global error:
Cannot find switch master cell for instance I2 in cellView (inv layout) from viewlist 'auLvs cmos_sch schematic symbol ' in library 'Test'.
global error:
Cannot find switch master cell for instance I3 in cellView (inv layout) from viewlist 'auLvs cmos_sch schematic symbol ' in library 'Test'.
global error:
Cannot find switch master cell for instance I4 in cellView (inv layout) from viewlist 'auLvs cmos_sch schematic symbol ' in library 'Test'.
si: Netlist did not complete successfully.
End netlist: Apr 9 17:40:27 2019
Comparison program did not complete.