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Help in Verilog-A with cadence virtuoso

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MahmoudHassan

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Hi all ,
In book Verilog-AMS he is providing an example of a listing that can use another previously developed module by using statement ' include "moduleName.vams"
I tried to use this in cadence virtuoso by copying the previous module in the same cell or even in the discpline.vams directory but still he could find my previously developed module and giving me an error he couldn't find it

any help how to point in my code to add another module using include statement like that one i am sharing from the book.

xxx.JPG

Best Regards,
Mahmoud
 

What simulator do you use ?

“resistor” and “vsrc” are both primitives of spice type simulator.
So you don’t have to include them.

Surely see logfile of simulator you use.
 
That's what exactly I did
I created a library and cell with a view of VerilogA
then enclosed the cell with a symbol (not in this case as when I closed the project it gave me an error for the include statement)

then I a create a test cell add this symbol with voltages to test it using the ADE-L using Spectre
 

What if i want to include just another module I developed, not a voltage source may be another block
How can I include it in my code?
 

As far as you use Cadence Spectre Netlister from Cadence ADE, you don’t have to include anything.
Surely see ahdl_include statement in generated Spectre netlist.
 
Would you mind sharing an example/tutorial of using ahdl_include statement in virtuoso?
 

Would you mind sharing an example/tutorial of using ahdl_include statement in virtuoso?
You can not understand virtuoso.
Virtuoso is a design framework.
There is no relation to ahdl_include statement.
 
I understand that I am using virtuoso only as a framework
I mean when creating a cell view of verilog-A in library manager inside virtuoso How can I include another module inside my Verilog-A code?
 

If you want to use the veriloga view, you have to (or I
had to, back when I worked for a company that paid
Cadence's ransom) make a veriloga view (copy the
symbol) and bind the verilog.va code to it, and use
the Hierarchy Editor or your search view list priority /
stop view list priority to get the veriloga view instead
of the symbol view (and its referenced model) to play.
You would be best off running Spectre from the top
level config view and using Hierarchy Editor (which
will spawn if you let it) to pick -which- veriloga and
-which- spectre views to use, unless it's all very uniformly
one or the other (unlikely).
 

I understand that I am using virtuoso only as a framework
I mean when creating a cell view of verilog-A in library manager inside virtuoso How can I include another module inside my Verilog-A code?
Create cell which you want to instantiate in other Verilog-A module.

See pll/veriloga, phase_detector, vco, lpf_1storder in ahdlLib.
 
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