Parking lot occupancy counter State Diagram

eengr · Apr 5, 2019

Hi I am working on this problem using VHDL design

It requires two inputs as two sensors (A & B) (as shown in the pdf attached)

View attachment Parking lot occupancy Counter.pdf

It has two outputs as ENTER_CAR & EXIT_CAR. They need to be asserted for ONE clock cycle depending upon if car is entering or leaving.

I have done the state diagram for this (as shown in the pdf attached)

Where I am struggling is the YELLOW HIGHLIGHTED 'ms_tick = 1' condition that takes the State-4 or State-8 back to State-0

I can generate this tick by using a counter but that will cause the OUTPUTS ENTER_CAR & EXIT_CAR to stay asserted for more than one clock cycle.

Is there a VHDL synthesizeable statement that I could use to check for 1 clock cycle and could be used to get out of these states?

TrickyDicky · Apr 5, 2019

Why not just create the tick on detecting the change of states?

eengr · Apr 5, 2019

I have done the following mod:

Where I now generate the output ticks when changing the state from State-3 to State-0 OR State-7 to State-0.

But problem I have is that depending upon when the state changes

IF the state changes on falling edge of my clock then, I get the output tick for HALF a Clock only

If the state changes on rising edge of my clock then, I get the output tick for FULL clock cycle.

Is there a way to get around this so that I get output tick for full clock cylce?

TrickyDicky · Apr 5, 2019

Yes only use the rising edge. You cannot use two edges in an FPGA anyway

eengr · Apr 5, 2019

Ok I think I am still confused here.

Here is my code:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity parking_lot is
    generic(N : integer := 3); --2^N * 20ns = 10ms - change it to 19
    Port ( clk, reset : in  STD_LOGIC; 
              a_frnt : in  STD_LOGIC;
           b_bck : in  STD_LOGIC;
              count_out : out STD_LOGIC_VECTOR(N-1 downto 0);
              tick_out : out STD_LOGIC;
           enter_car : out  STD_LOGIC;
           exit_car : out  STD_LOGIC);
end parking_lot;
 
architecture Behavioral of parking_lot is
    
    constant DVSR : integer := 1; -- no of 20ns cycles to generate 10ms tick Change this to 500000
    signal q_reg, q_next : unsigned (N-1 downto 0) := (others => '0');
    signal ms_tick : std_logic := '0';
    
    type eg_state_type  is (state0, state1, state2, state3,
                                    state5, state6, state7);
    signal state_reg, state_next : eg_state_type;
 
begin
 
    count_out <= std_logic_vector (q_reg);
    tick_out <= ms_tick;
    
    -- *********************************************
    -- Counter to generate 10ms tick
    -- *********************************************
    process (clk, reset)
    begin
        if (reset = '1') then
            q_reg <= (others => '0');
        elsif (clk'event and clk = '1') then
            q_reg <= q_next;
        end if;
    end process;
    
    -- next state logic
    q_next <= 
                (others => '0') when q_reg = DVSR OR reset = '1' else
                q_reg + 1;
    -- 10 ms_tick   
    ms_tick <= '1' when q_reg = DVSR else '0';
    
    
    -- *********************************************
    -- Car Enter/ Exit FSM
    -- *********************************************
    process (clk, reset)
    begin
        if (reset = '1') then 
            state_reg <= state0;
        elsif (clk'event and clk = '1') then
            state_reg <= state_next;
        end if;
    end process;
    
    -- next state logic & Output logic
    
    process (state_reg, a_frnt, b_bck, ms_tick)
    begin
        state_next <= state_reg; -- default back to same state
        enter_car <= '0'; -- default is 0
        exit_car <= '0'; -- default is 0
        
        
        case state_reg is
            when state0 =>
                if (a_frnt = '1' AND b_bck = '0') then
                    state_next <= state1;
                elsif (a_frnt = '0' AND b_bck = '1') then
                    state_next <= state5;
                end if;
                
            when state1 =>
                if (a_frnt = '0' AND b_bck = '0') then
                    state_next <= state0;
                elsif (a_frnt = '1' AND b_bck = '1') then
                    state_next <= state2;
                end if;
                
            when state2 =>
                if (a_frnt = '0' AND b_bck = '0') then
                    state_next <= state0;
                elsif (a_frnt = '0' AND b_bck = '1') then
                    state_next <= state3;
                end if;
                
            when state3 =>
                if (a_frnt = '0' AND b_bck = '0') then
                    enter_car <= '1';
                    state_next <= state0;
                end if;
            
--          when state4 =>
--              enter_car <= '1';
--              if (ms_tick = '1') then
--                  state_next <= state0;
--              end if;
                
            when state5 =>
                if (a_frnt = '0' AND b_bck = '0') then
                    state_next <= state0;
                elsif (a_frnt = '1' AND b_bck = '1') then
                    state_next <= state6;
                end if;
                
            when state6 =>
                if (a_frnt = '0' AND b_bck = '0') then
                    state_next <= state0;
                elsif (a_frnt = '1' AND b_bck = '0') then
                    state_next <= state7;
                end if;
                
            when state7 =>
                if (a_frnt = '0' AND b_bck = '0') then
                    exit_car <= '1';
                    state_next <= state0;
                end if;
                
--          when state8 =>
--              exit_car <= '1';
--              if (ms_tick = '1') then
--                  state_next <= state0;
--              end if;
                
                
                
                
        end case;   
                
                
                    
    
    end process;
    
 
 
end Behavioral;

My test bench code is:

Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb1 IS
END tb1;
 
ARCHITECTURE behavior OF tb1 IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT parking_lot
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         a_frnt : IN  std_logic;
         b_bck : IN  std_logic;
         count_out : OUT  std_logic_vector(2 downto 0);
         tick_out : OUT  std_logic;
         enter_car : OUT  std_logic;
         exit_car : OUT  std_logic
        );
    END COMPONENT;
    
 
   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal a_frnt : std_logic := '0';
   signal b_bck : std_logic := '0';
 
    --Outputs
   signal count_out : std_logic_vector(2 downto 0);
   signal tick_out : std_logic;
   signal enter_car : std_logic;
   signal exit_car : std_logic;
 
   -- Clock period definitions
   constant T : time := 20 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
   uut: parking_lot PORT MAP (
          clk => clk,
          reset => reset,
          a_frnt => a_frnt,
          b_bck => b_bck,
          count_out => count_out,
          tick_out => tick_out,
          enter_car => enter_car,
          exit_car => exit_car
        );
 
   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for T/2;
        clk <= '1';
        wait for T/2;
   end process;
    --*************
    -- reset 
    --************* 
 
    reset <= '1', '0' after T/2;
 
 
   -- Stimulus process
   stim_proc: process
   begin        
      wait until falling_edge(clk);
        --****************************
        -- No car
        --****************************
        
        a_frnt <= '0';
        b_bck <= '0';
        for i in 1 to 3 loop
            wait until falling_edge(clk);
        end loop;
        
        --**********************************************************
        -- car enters block a_frnt sensor
        --**********************************************************
        
        a_frnt <= '1';
        b_bck <= '0';
        for i in 1 to 3 loop
            wait until falling_edge(clk);
        end loop;
        
        --**********************************************************
        -- car enters block a_frnt sensor & b_bck sensor
        --**********************************************************
        
        a_frnt <= '1';
        b_bck <= '1';
        for i in 1 to 3 loop
            wait until falling_edge(clk);
        end loop;
        
        --**********************************************************
        -- car enters un-block a_frnt sensor & blocks b_bck sensor
        --**********************************************************
        
        a_frnt <= '0';
        b_bck <= '1';
        for i in 1 to 3 loop
            wait until falling_edge(clk);
        end loop;
        
        --**********************************************************
        -- car enters un-block a_frnt sensor & un-blocks b_bck sensor
        --**********************************************************
        wait for 10ns;
        a_frnt <= '0';
        b_bck <= '0';
        for i in 1 to 3 loop
            wait until falling_edge(clk);
        end loop;
        
        
        --******************************
      --terminate Simulation
      --******************************
 
        
 
        assert false
        report "NS Simulation Completed"
        severity failure; 
   end process;
 
END;

I did two simulations one with the test bench as above. Other with line-120 (wait for 10ns) commented out

My simulation results with line-120 (wait for 10ns) commented out are:

My simulation results with test bench same as above are:

As it can be seen that 'enter_car' is ON for 1/2 clock cycle for 1st picture
& full-clock cycle for 2nd picture

This is what I am confused about as in what I am doing wrong here (what do I need to do to get the enter_car asserted for FULL Clock cycle)

TrickyDicky · Apr 5, 2019

Its probably because enter_car is a combinatorial output, and in state 3, if a_front and b_front are '0', enter_car will be '1'.

It would probably make more sense if you registered all the outputs and created a single process state machine, rather than 2 process.

wwfeldman · Apr 5, 2019

change state only on rising edge of a clock
ms_tick is set to 1 or 0 depending on the state, and must last for 1 clock cycle

state diagram from your second post:
states 1, 2, 5 and 6 look like no-operation states. move one (say state 2) to between state 3 and state 0 to assert enter_car for 1 clock cycle
likewise, move one (say state 6) to between state 7 and state 0 to assert exit_car for 1 clock cycle

you may want to re-assign state designation numbers to maintain the one bit change

eengr · Apr 5, 2019

TrickyDicky said:
It would probably make more sense if you registered all the outputs and created a single process state machine, rather than 2 process.

What do you mean by 'registered all the outputs'?

Do you mean combine the
process (clk, reset) & process (state_reg, a_frnt, b_bck, ms_tick)

to something like this:

process (clk, reset, state_reg, a_frnt, b_bck, ms_tick)

TrickyDicky · Apr 5, 2019

no. Remove the state_next signal entirely. And use the following pattern:

Code VHDL - [expand]
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process(clk, reset)
begin
 
  if reset = '1' then 
    state_reg   <= state0;
    
  elsif rising_edge(clk) then
    case state_reg is
      when state0 => 
        ....
        state_reg <= state1;
      
      when state1 => 
        ....
        state_reg <= state2;
        
      --- etc
  
  end if;
end process;

eengr · Apr 5, 2019

TrickyDicky said:

no. Remove the state_next signal entirely. And use the following pattern:

Code VHDL - [expand]
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process(clk, reset)
begin
 
  if reset = '1' then 
    state_reg   <= state0;
    
  elsif rising_edge(clk) then
    case state_reg is
      when state0 => 
        ....
        state_reg <= state1;
      
      when state1 => 
        ....
        state_reg <= state2;
        
      --- etc
  
  end if;
end process;

Fantastic that works

Thank you very much. Now I am going to look into following advice as it looks like it would help me to reduce the number of states

wwfeldman said:
change state only on rising edge of a clock
ms_tick is set to 1 or 0 depending on the state, and must last for 1 clock cycle

state diagram from your second post:
states 1, 2, 5 and 6 look like no-operation states. move one (say state 2) to between state 3 and state 0 to assert enter_car for 1 clock cycle
likewise, move one (say state 6) to between state 7 and state 0 to assert exit_car for 1 clock cycle

you may want to re-assign state designation numbers to maintain the one bit change

eengr · Apr 9, 2019

wwfeldman said:
state diagram from your second post:
states 1, 2, 5 and 6 look like no-operation states. move one (say state 2) to between state 3 and state 0 to assert enter_car for 1 clock cycle
likewise, move one (say state 6) to between state 7 and state 0 to assert exit_car for 1 clock cycle

you may want to re-assign state designation numbers to maintain the one bit change

Thanks, that worked with two states taken out

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Parking lot occupancy counter State Diagram

eengr

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