Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If you are doing LEC between rtl and netlist hierarchical lec is recommended since it works and divide and conquer strategy. Flat lec will be time consuming especially if the design is huge. For netlist to netlist comparison flat can be done.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
