Input common mode range simulation for fully differential amplifier

Dear friends,

I have simulated the ICMR of my fully differential amplifier by using the STB analyses with the help of diffstbprobe, I swept the input common mode voltage from rail to rail and looking to the output gain and GBW.
I am using PMOS and NMOS stage to have rail to rail ICMR,

it is supposed by theory, that there is region where either PMOS or the NMOS stage will be off so the gain as well as the GBW will change by factor of two, this is the reason why people use the constant gm technique in their design to make it constant as much as possible,

However, in my design I didn't use any gm constant technique and still have almost constant gain or GBW overall the range as you kindly can see from the simulated result below... do you think it is possible ?



Thank you in advance

Your schematic?

hello !
Can you explain how do you run this simulation, I want to know how you ran input common mode simulation

I am connecting the amplifier as normal as how to test the AC characteristics by using stable loop from STB and diffstbprobe. Then I run the AC simulation and sweep the ICMR DC voltage and record the AC gain, GBW over the ICMR

Junus2012 said:

I am connecting the amplifier as normal as how to test the AC characteristics by using stable loop from STB and diffstbprobe. Then I run the AC simulation and sweep the ICMR DC voltage and record the AC gain, GBW over the ICMR

Click to expand...

I usually find ac gain nad phase of an amplifier using AC analysis and dont use STB to run it. Is there any written manual to understand STB analysis.

Dear msri

I will tell you how, just tell me is your amplifier is fully differential or single ended output

I would not look to stb analysis as a guarantee of suitable
operation, for ICMR design:spec closure.

Small signal analysis doesn't tell you things like, are you
clipping to the point that output distortion and gain-
falloff have made the application-circuit outcome useless.

If by "input common mode range" you mean the range
across which the device meets -all- data table performance
limits, that wants a lot more wringing-out. Things like gain,
PSRR, CMRR all get a lot worse when you are against the
rails, input or output, unless you have cute stuff like
beyond-the-rails internal charge pump fed supplies or
a double-everything rail-rail input architecture (output,
still doesn't like the final FETs going linear-region much).

Simulating response is easy. Asking the right questions
and appropriately criticizing the setup and the outcome,
that's more exhausting and tricky (you can make it easy
on yourself and hard on the eventual user, or vice versa).

Of course if there is no actual user and only one
parameter of interest, things get a lot simpler. I'd still
go with inspection of large signal time domain results
in an application-realistic testbench if it were me.

Dear freebird,

First I thank you for your reply,

I am using the Stability analyses because I want to simulate the GBW and the AC gain,, which give me no other solution rather than running the AC simulation or the STB counterpart.

You asked me about what I mean by the input common mode range,

I mean the range of the DC common mode voltage where the transistors are still in saturation. There are two methods as you surely know, the first method is connecting the amplifier as a unity gain buffer and from DC analyses by sweeping the input and recording the output. The linear range is then definded at the linear portion of the output. However this simulation need to monitor the current of the tail transistors. This simulation will not give information about the GBW or gain variation over the entire range of ICMR.

Second method is also proposed by Allen Holberg, is by running the AC simulation and sweeping the common mode DC voltage and recording the AC gain and or the GBW, thus we can discover the ICMR from the AC gain or GBW plot. The disadvantagues of this method is when you sweep the DC common mode voltage, the offset voltage of the amplifier will also change and if I am simulating with open loop feedback configuration then my hole setup will fail. A solution is by using STB which use stable feedback to give accurate result of AC charasterictics regardless of the offset voltage

Thank you once again