[SOLVED] RGMII problem with MAX 10 Development board

Hello,

I'm trying to create my own RGMII interface for the MAX 10 Development Kit.
Until now I was working with the Cyclone 10 LP Evaluation Kit, I sucesfully created an RGMII following this intel manual:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an477.pdf

Now I wanted to adapt my project to this new MAX 10 board, but it is not working. So I guess that the RGMII PHY of this new board doesn't have the same skew configurations. I'm not able to find any information about that, in the Cyclone LP board I was able to find that for RX the delay is already implemented inside the physical chip, for Tx it's not so I used a PLL to displace the clock phase 90º.

As I don't really know where is the problem, my plan was to just try to center-align the Rx clock, and see if I start receiving something. But I can't connect a non-dedicated clock pin to the PLL, so I can't repeat the previously done for Tx.

Any ideas on how to do that? And also any idea about the skew configuration of that specific board? (It uses the Marvel 88E1111 chip).

Also the manual says that "You can achieve this with a DLL and by assigning RX_CLK to a DQS pin or promoting RX_CLK to a global or regional net if you need a small clock latency." But the RX_CLK pin is already set in the FPGA. I don't get it 100%.

Try using SignalTap logic analyzer to see if you can receive something.
And the 88E1111 chip is hard to use because there is no public documentation for it. You have to pay and sign NDA to get any information about config. registers etc.

88e1111 should also have a tx skew option I think. You might have to look at linux kernel modules to find the reverse-engineered register map. (I think the map isn't complete for all features of the 88e1111, but I recall it having useful info.)

--edit: actually, I don't know if the register map was reverse engineered. I guess Marvell might have released the mapping of the most commonly used registers.

As I don't really know where is the problem, my plan was to just try to center-align the Rx clock, and see if I start receiving something. But I can't connect a non-dedicated clock pin to the PLL, so I can't repeat the previously done for Tx.

Click to expand...

In the data sheet for 88E1111 there should be a register which will allow you to vary the RGMII Rx clock edge. By varying the bits of that register, you can play around with nano-sec resolution delay and find the best values to center-align the Rx clock. I had done it with the 88E1510 RGMII PHY.

And the 88E1111 chip is hard to use because there is no public documentation for it. You have to pay and sign NDA to get any information about config. registers etc.

Click to expand...

That's true, get the proper data sheet after NDA.

dpaul said:

In the data sheet for 88E1111 there should be a register which will allow you to vary the RGMII Rx clock edge. By varying the bits of that register, you can play around with nano-sec resolution delay and find the best values to center-align the Rx clock. I had done it with the 88E1510 RGMII PHY.

Click to expand...

Thanks you very much for all the answers. I've found the register you mention. As you all have commented I had to first get the NDA Datasheet. I haven't try it yet, but I guess that this will solve my problem.

Thanks again.