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Parent signal when alias is accessed

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shaiko

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Hello,

While debugging an old design I came across the following code:

Code: 
alias x : std_logic is y ( 18 ) ; -- y is a 32 bit wide std_logic_vector input port.

begin

process ( clock ) is 
begin 
  if rising_edge ( clock ) then
     if x = '1' then
        some_other_signal <= a + b ;
        [COLOR="#FF0000"]x <= '0'[/COLOR] ;
     end if ;
  end if ;
end process ;
Question:
Why does this code even compile ? To me it seems that the line marked in red cause 'x' to be driven by 2 drivers...
What am I missing here ?
 

edit - just seen the input port comment

No Idea, that should indeed be an error. You say old code? maybe old code with bad old compilers.
 
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    shaiko

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And what if Y was driven by another process of the same architecture ?
Will this be legal ?
 

depends if y(18) was driven in the other process. Each element of an array (or record) can be driven from a different process.
 

depends if y(18) was driven in the other process
Click to expand...
If it was then driving x<='0' would also reset y (18) ??
Why would anyone write such code?? It "hides" logic and hurts the readability...
 

shaiko said:
If it was then driving x<='0' would also reset y (18) ??
Why would anyone write such code?? It "hides" logic and hurts the readability...
Click to expand...

No, it would not reset Y, it would create multiple drivers.
No Idea why it was done like that - speak to the engineer responsible.
 
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    shaiko

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I could possibly see if this wasn't std_logic_vector but rather something that had a synthesizable wired-and resolution function.

The other possibility is that the name of the alias is similar to the name of another signal and you've simply mistaken them.

The third thought is that the optimizer finds that x = 0 is always true and just ignores this code as unreachable. (or that some_other_signal is unused or always assigned to the same expression, making the multiple drivers a non-issue)
 
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    shaiko

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