Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Need help with VCS part compilation

Status
Not open for further replies.
G

Groh

Newbie level 1
Joined
Mar 26, 2019
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
8
Hello,

I am using part compilation in VCS to compile RTL and std cells in separate library files. Even though all the lib cells are compiled and included in liblist, I am getting error for some cells saying definition not found during elaboration stage.
I have some library files and rtl files which I compiling using vlogan.

Analysis:
vlogan -work L1 -f lib_cell.f
vlogan -work L2 -f rtl.f
vlogan -work L3 lib_cell_1.v
vlogan -work L4 func.v
vlogan -work TOP_LIB top_rtl.v
vlogan -work work -ntb_opts uvm-1.1 -sverilog tb_top.v(and other tb files) -top test
vlogan -work work tb_cfg.v
Click to expand...

Elaboration:
vcs work.top_cfg
Click to expand...

Simulation:
./simv
Click to expand...

tb_cfg.v contains:
config top_cfg
work.test
default liblist L1 L2 L3 L4 top_lib ;
endconfig
Click to expand...

synopsys_sim.setup file:
WORK > DEFAULT
DEFAULT : ./work
TOPLIB : ./top_lib
L1 : ./l1
L2 : ./l2
L3 : ./l3
L4 : ./l4
Click to expand...

Can someone please help me with this.

Thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top