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[SOLVED] Using if-else generate to make dynamic hardware implementation using FPGA

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MSAKARIM

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can i use if-else generate in real world?
can an FPGA be reconfigured according to some inputs from user ?
i make three components and i need to implement component 1 while some input called (level=1), implement component 2 when (level=2), implement component 3 when (level=3) and implement component 4 when (level=4). where input (Level) is taken from the user
I used ( if else generate) supported by VHDL-2008 and make Level is generic < but i need it to be an input taken from user.
 

What do you mean by "input from a user"? Generates use constant values to create the conditional code. IE. these values must be known at compile time. They cannot change during run-time (as that would be like re-configuring your circuit board while it is turned on).

On the subject of the actual code:

IF generate has been supported for a long time.
If-else-generate (and case generate) is part of VHDL 2008, and has less support from vendors.

It has been available for some time in Vivado.

But there is nothing wrong with if generate if you are careful and creating mutually exclusive branches:
for example this:

Code VHDL - [expand]
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gen1 : if SOME_CONDITION generate
   ....
 
else generate
 
end generate gen1;


can be written in 93 style

Code VHDL - [expand]
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gen1 : if SOME_CONDITION generate
    ..
end generate gen;
 
gen2 : if not SOME_CONDITION generate
  ...
end generate gen2;


Just be careful there are no overlaps in your generate conditions. THis form has been used for many years.
 
I think the OP wants to do dynamic reconfiguration. But then again, I can't be sure...
 
I am assuming that the OP has understood that in post#2, the SOME_CONDITION must be specified during compile time (synth & impl)

some inputs from user
Click to expand...
.....when? At run time or compile time?

But then by this statement
I used ( if else generate) supported by VHDL-2008 and make Level is generic < but i need it to be an input taken from user.
Click to expand...
, I think the OP means changing something when the design is running. In that case he should look at dynamic reconfiguration. For Xilinx FPGAs it requires a special license.

btw - What is your idea regarding taking an input? Can you please make it clear?

A top level generic can also be changed by an user and then one can go for synth & impl. Or do you mean when the bitstream is running in FPGA, then user wants to input something and based on that something happens to the design that that is running?
 
Last edited:
I assume that the question is about changing the function in runtime.
I there is enough resources in the FPGA, the first choice should be to use muxes to switch between the functions.
If that doesn't work, partial or complete reconfiguration can be used, but it is more complicated.

In either case, "if-else generate" alone can't be used to change the function in runtime.
 
Firstly, thanks for your help
Yes i need to change the function in run-time. Is it possible?

- - - Updated - - -

Thanks for your help.
Is dynamic reconfiguration can change the function that be implemented in fpga in run-time?

- - - Updated - - -

Thank you so much
"user wants to input something and based on that something happens to the design that that is running?"
yes for your question, i need this exactely.
 

Dynamic reconfiguration can't solve the problem either. It involves complete reconfiguration of the FPGA core, only keeping the IO configuration.

Having alternative functions in a FPGA can be achieved by instantiating all components and implement muxes that select between alternative signals.
 
thank you so much
for this solution>> "there is enough resources in the FPGA, the first choice should be to use muxes to switch between the functions." i tried it but it consumes more time and power.
can i make partial reconfiguration in FPGA? can i divide it to make more than function and switching between them during run-time BUT without implementing all of them at one time. I need to change function during run-time
 

Then I suggest this is a design problem.
Dynamic reconfiguration is something very few people use. Usually you just implement all possible functions and switch between them.
Have you assesed if any functions (or parts of functions) can be re-used for other functions?
Have you looked into making parts more resource efficient?

if you want more detailed help you will need to ask a more detailed question.
 
In my design I have three functions for ex. (A,B and C). I need when implementing A no time or power are consumed to implement B and C also. This is a condition enhances my design idea.
Is dynamic configuration helping me to switch between A , b and C without need to implement (B and C) while implementing A
Is this clear or give more explanation?
 

MSAKARIM said:
In my design I have three functions for ex. (A,B and C). I need when implementing A no time or power are consumed to implement B and C also. This is a condition enhances my design idea.
Is dynamic configuration helping me to switch between A , b and C without need to implement (B and C) while implementing A
Is this clear or give more explanation?
Click to expand...

this is what dynamic reconfiguration was invented for. just remember that in the end you need an (external) memory to store 3 bitstreams instead of 1, and with that comes a cost.
 
MSAKARIM said:
In my design I have three functions for ex. (A,B and C). I need when implementing A no time or power are consumed to implement B and C also. This is a condition enhances my design idea.
Is dynamic configuration helping me to switch between A , b and C without need to implement (B and C) while implementing A
Is this clear or give more explanation?
Click to expand...

Why would implementing 3 functions, but having only one active at a time consume more power? If you’re not clocking the other two functions, there shouldn’t be any significant difference in power. And what does ‘consuming time’ mean?
 
barry said:
Why would implementing 3 functions, but having only one active at a time consume more power? If you’re not clocking the other two functions, there shouldn’t be any significant difference in power. And what does ‘consuming time’ mean?
Click to expand...


I need to switch between these three function during run-time, but without using mux to switch between, as mux makes them all implemented (while only one NOW needed).

- - - Updated - - -

ThisIsNotSam said:
this is what dynamic reconfiguration was invented for. just remember that in the end you need an (external) memory to store 3 bitstreams instead of 1, and with that comes a cost.
Click to expand...

Thanks for Ur help, yes exactely this is what i mean
I found that " https://www.youtube.com/watch?v=ftO1AylNB0M " is this helpfull?
 

MSAKARIM said:
I need to switch between these three function during run-time, but without using mux to switch between, as mux makes them all implemented (while only one NOW needed).

- - - Updated - - -



Thanks for Ur help, yes exactely this is what i mean
I found that " https://www.youtube.com/watch?v=ftO1AylNB0M " is this helpfull?
Click to expand...

Dynamic reconfiguration is NOT THE same as 'switching between functions'. It is NOT switching during run-time. Dynamic reconfiguration is reloading the FPGA and starting from scratch.
 
MSAKARIM said:
I need to switch between these three function during run-time, but without using mux to switch between, as mux makes them all implemented (while only one NOW needed).
Click to expand...

You can have separate clock nets for the 3 blocks, then you can eliminate the current consumption from the unused blocks.
If you have enough resources in the FPGA, the mux solution is probably the best.
It is much easier to implement than something based on reconfiguration.
The switching with muxes is very fast.
Swiitching using full or partial reconfiguration takes much longer time. Assume that the reconfiguration can take a few seconds.
 
The OP wants either partial reconfiguration or multiple bitstreams. I doubt we will get enough information to provide advice or even determine if this is needed/useful.

For multiple bitstreams, if-generate can be used and top-level generics can be set for each of the multiple builds.
For partial reconfiguration, the OP would need to read the documentation. I remember PR having many restrictions and requirements.

--edit: clock switching would also be possible and easy. I just have a suspicion that the OP won't go for it.
 
Hi,

I'm with barry.
I'd also code everything in one configuration in one file and just switch the functions.

One file, fastest selection between different functions.

In detail it depends on your requirements.
But we don't know the complexity of your functions, nor do we know what are all the I/Os, nor do we know which PLD you use.

Klaus
 
Partial reconfiguration has come up where I work.
After investigation, the result was its just a pain, too restrictive, and difficult to get support on it even from Xilinx. Like most new things, the hype never quite matches reality. Those that use it probably love it, but as Ive seen from other ground breaking ideas (HLS) those people probably had a lot of work to get there.
So we stick with "muxes", or just completely separate variant builds.
 
For me, PR never even got that far. IMO, that was Xilinx's fault. They made PR a licensed feature. That basically killed it off every place I worked. FPGA is already niche, PR is super-niche. Making the tech hard to access killed it for me and the places I worked.

I don't think Xilinx cares that much about PR anyways though. Configuration bandwidth has remained constant for a decade while device size hasn't.
 
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