Poomagal
Newbie level 6
To find modular inverse value, I found the availability of Binary/Extended Euclidean algorithm.I have written the synthesizable code for this algorithm. But while i execute the testbench, I cannot get the output and also its got hanged-on and i need to power off the system without proper shutdown. Please help me to find and solve this error. FYI, I have attached the verilog code which I have written to analyse it.
verilog code:
verilog code:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 module modinv( input [7:0] a, input [7:0] p, output [7:0] out ); reg [7:0]u; reg [7:0]v; reg [7:0]x; reg [7:0]y; reg [7:0]x_y; reg [7:0]y_x; wire u_is_one; wire v_is_one; always @(*) begin //step 1 x=8'd1; y=8'd0; //step 2 u<=a; v<=p; //step 3 while (u!=1 && v!=1) begin //step 3.1 //First condition while (u[0]==0) begin u<=u/2; if (x[0]==0) x<=x/2; else x<=(x+p)/2; end//step 3.1 ends //step 3.2 //second condition while (v[0]==0) begin v<=v/2; if (y[0]==0) y<=y/2; else y<=(y+p)/2; end//step 3.2 ends here //step 3.3 //Third condition if (u>=v) begin u<=u-v; x_y<=x-y; x <= x_y - p * (x_y/p); end else begin v<=v-u; y_x<=y-x; y <= y_x - p * (y_x/p); end//step 3.3 ends here end//while ends end assign out=(u==8'd1)?x:y; endmodule module tb_modinv; // Inputs reg [7:0] a; reg [7:0] p; // Outputs wire [7:0] out; // Instantiate the Unit Under Test (UUT) modinv uut ( .a(a), .p(p), .out(out) ); initial begin // Initialize Inputs //a = 0; p = 0; #20 a=3;p=5; // Wait 100 ns for global reset to finish #100 $finish; // Add stimulus here end endmodule
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