[SOLVED] How to simulate a circuit with feedback with a test voltage after making a breakpoint

Hello everyone, there's a circuit that is in feedback that I believe is not one of the 4 feedback topologies. I'd like to simulate the feedback loop by putting a break point and inserting a test voltage, Vt, and get the output voltage Vo and measure the feedback loop, Vo/Vt. as seen in the attached figure as an example.



However, if put a break point, would that mean that I need an appropriate value for Vt for the the circuit to function properly (as if the break point didn't exist in the first place)? What are your comments in this method?

You must break the loop at a point where the load is rather large (e.g. at the gate input) - otherwise the loop gain is not correct (because the load is present under closed-loop conditions).
More than that. the breaking must not change the normal DC operating point.

A better breaking point would be at the gate of the NMOS in the left branch of your circuit. Of course, the type of the feedback will depend on where you take your output from, which you don't show in your drawing, but assuming it is between the drains of the PMOS and NMOS in the folded branch (right branch in your drawing), then you can consider it as shunt-series, that is shunt at the output and series at the input.

Anyway, you can insert a voltage source in series at the break point. The side of the v.source facing the gate of the left branch NMOS is the input stimulus and the return voltage is the voltage at the other side of the v.source - both with respect to ground. Take the ratio and that's your loop gain, at least for low frequencies. This is part of the Middlebrook's method for testing stability.
If you're using cadence, best to break the loop with an iprobe and do stb analysis.

You must break the loop at a point where the load is rather large (e.g. at the gate input) - otherwise the loop gain is not correct (because the load is present under closed-loop conditions).

Click to expand...

Yes I realized this a while later. In this situation, would it be a good idea to replace the test voltage, Vt, to a test current, It, for a low input impedace such as the source of the PMOS transistor?

More than that. the breaking must not change the normal DC operating point.

Click to expand...

This is what I meant when I said "an appropriate value for Vt", should the DC value for Vt be the normal operating value of the node before breaking the loop?
Here were my steps:
1. Simulate the complete circuit and find the node voltages or branch currents.
2. Break the loop at the gate (or source) and add a test voltage (or current) with a DC value of the node voltage (or branch current).
3. Add an AC signal to Vt (or It) and plot Vo/Vt (or Vo/It).

Thoughts on this procedure?

Here are two acceptable methods of simulating the loop gain (approx results at high frequencies) that will keep the dc operating point intact but will give you the loop gain T. In the first case, your stimulus faces very big impedance looking into the gate. In the second case your current stimulus faces low impedance (1/gm).

In order to ensure that the normal DC operating point does not change, using the node voltages from a previous DC op simulation might not be enough. For example, of your loop gain is 1000 and you set 1V instead of 0.999V you will have a massive error!
Also, you are not capturing the loading effect of the break point (the capacitance at the gate, etc)

The two possible methods are:
1. Have three parallel circuits like shown below. A for DC operating Point, C Loading and B for actual loop gain measurement.


Since this is measuring the loop characteristics with loading and at the correct operating point, this method would be valid always. I.e. There are no assumptions here.

2. If you are using Cadence Virtuoso, use STB analysis. This does the same as above without much effort.

PS Not sure why the image is rotated.

Actually, stb in cadence doesn't do this thing, in fact, it is very far from this thing.

This is the same approach I used a lot for my LDO designs before I knew about the STB analysis.

sutapanaki said:

Actually, stb in cadence doesn't do this thing, in fact, it is very far from this thing.

Click to expand...

Hi,

Could you elaborate on the Cadence STB analysis or point me to some resources on the same. I would like to read more on this. Thanks...

You can read an article called "Striving for small-signal stability". Basically, cadence's iprobe stb measurement uses Middlebrook's method for feedback stability but with some modifications.