Clock cells adding jitter to clock

do clock cells on the clock path add to jitter?

For every clock cell we add on the clock path, we are adding random latency through it. And different clocks on different clock path could have very different jitter?

1. won't this make the jitter on the clock much worse?
2. does this also add uncertainty to the skew?

jitter, skew, and latency are concepts that are completely misunderstood and mislabelled. some people call jitter what is actually uncertainty. some people bin all the effects of process variation into jitter... and so on.

what you really need to know is that all forms of jitter, skew, and latency are accounted by the clock tree synthesis tool. your assertion is correct that every cell you add to the tree may create delays with an almost random characteristic (due to process variation).

"It depends".

Much jitter is injected from the power / ground nets,
across the edge risteime as a voltage->time transform.
Fast edges accrue less jitter per supply deflection
(but also impose more internal noise on those rails,
and the localization of noise is a thing, as the noise
creators are going to differ with local functionality).

If you consider the supply voltage noise to be the
main actor in this way, there is going to be some
cancellation (where supply moves threshold up,
that speeds HL and slows LH, so subsequent stage
may cancel some jitter-push). But supply-span
compression adds delay at every stage and so,
a jitter component.

In the end there's only so much you can squeeze
out of a clock tree before you lose top end, and an
optimum well before that.

ThisIsNotSam said:

jitter, skew, and latency are concepts that are completely misunderstood and mislabelled. some people call jitter what is actually uncertainty. some people bin all the effects of process variation into jitter... and so on.

what you really need to know is that all forms of jitter, skew, and latency are accounted by the clock tree synthesis tool. your assertion is correct that every cell you add to the tree may create delays with an almost random characteristic (due to process variation).

Click to expand...

So in this case, this uncertainty due to PVT on clock cells is accounted by the 'margin'?

What margin? The PVT-related influence on the clock tree is calculated thoroughly for all cells under all corners. This is not directly marginated by the user.

ThisIsNotSam said:

What margin? The PVT-related influence on the clock tree is calculated thoroughly for all cells under all corners. This is not directly marginated by the user.

Click to expand...

So how is this uncertainty in the clock cells modeled and accounted for when we do timing?

By using the AOCV files that come with the std cell library.