JLHW
Member level 1
Hi, I'm quite new in analogue IC design and I'm currently designing a 0.13 um CMOS LNA that will operate at 60 GHz without bandwidth constraint. The PDK used is Silterra C13G. I'm currently using Synopsys Custom Compiler but may be switching to Cadence in the future (hence the title mentioning Cadence), and Synopsys is the only EDA that is currently available for me.
Silterra's built-in scalable spiral inductors could not achieve my inductance range (min 68 pH, max 104 pH) so I've chosen to create my own inductors with Sonnet.
I've managed to draw the inductors along with the exact tech layers from Silterra (confidential) from substrate until passivation layers, with 1mm of top air layer (GND layer is substrate WITHOUT air layer beneath it); successfully simulated them and achieved decent results, and extracted the IME files for both Synopsys and Cadence (.snp and .scs respectively). Besides, I've also exported the GDSII file of one of the inductors, and successfully imported it into Synopsys, but haven't perform DRC and LVS yet.
The problems are:
For both EDAs (and without Sonnet Cadence integration):
1. For the inductors, is there a way to link the respective model files and GDSII to a single cell respectively?
2. If (1) is possible, should I also manually assign a schematic symbol for each of the inductors?
3. If both (1) and (2) should/could be done, is it possible to reconnect all inductor cells to the main LNA circuit, and resume the regular IC design flow for both Synopsys and Cadence? Will there be conflict between the tech layers of my inductors and the main LNA circuit that already uses Silterra's PDK?
Sorry for the long post and thanks in advance.
Silterra's built-in scalable spiral inductors could not achieve my inductance range (min 68 pH, max 104 pH) so I've chosen to create my own inductors with Sonnet.
I've managed to draw the inductors along with the exact tech layers from Silterra (confidential) from substrate until passivation layers, with 1mm of top air layer (GND layer is substrate WITHOUT air layer beneath it); successfully simulated them and achieved decent results, and extracted the IME files for both Synopsys and Cadence (.snp and .scs respectively). Besides, I've also exported the GDSII file of one of the inductors, and successfully imported it into Synopsys, but haven't perform DRC and LVS yet.
The problems are:
For both EDAs (and without Sonnet Cadence integration):
1. For the inductors, is there a way to link the respective model files and GDSII to a single cell respectively?
2. If (1) is possible, should I also manually assign a schematic symbol for each of the inductors?
3. If both (1) and (2) should/could be done, is it possible to reconnect all inductor cells to the main LNA circuit, and resume the regular IC design flow for both Synopsys and Cadence? Will there be conflict between the tech layers of my inductors and the main LNA circuit that already uses Silterra's PDK?
Sorry for the long post and thanks in advance.
