AllenD
Member level 5
Hi Guys
I am using TSMC 65 nm PDK and I am working on I/O design. It came to my attention that I need to place a cell called power on control (POC), "to avoid the I/O unknown state during power-up. An unknown state might result in I/O crowbar current or bus contention when the I/O voltage is up before the core voltage." To the best of my understanding, POC power will be on only during the period when the IO power supply is on and core power is off.
My question is should I attach a pad to that cell and I have to manually add POC signal as in the attached pic(VDDPST is the I/O supply and VDD is the core supply)? Or the POC signal is created automatically?
My second question is what is the difference of "internal macro" vs "core"? Is "internal macro" refers to analog circuits and "core" refers to digital portion?
Thanks
Allen
I am using TSMC 65 nm PDK and I am working on I/O design. It came to my attention that I need to place a cell called power on control (POC), "to avoid the I/O unknown state during power-up. An unknown state might result in I/O crowbar current or bus contention when the I/O voltage is up before the core voltage." To the best of my understanding, POC power will be on only during the period when the IO power supply is on and core power is off.
My question is should I attach a pad to that cell and I have to manually add POC signal as in the attached pic(VDDPST is the I/O supply and VDD is the core supply)? Or the POC signal is created automatically?
My second question is what is the difference of "internal macro" vs "core"? Is "internal macro" refers to analog circuits and "core" refers to digital portion?
Thanks
Allen