+ Post New Thread
Results 1 to 3 of 3
  1. #1
    Member level 5
    Points: 850, Level: 6

    Join Date
    Aug 2017
    Posts
    82
    Helped
    0 / 0
    Points
    850
    Level
    6

    IC layout I/O design------power on control (POC) cell

    Hi Guys
    I am using TSMC 65 nm PDK and I am working on I/O design. It came to my attention that I need to place a cell called power on control (POC), "to avoid the I/O unknown state during power-up. An unknown state might result in I/O crowbar current or bus contention when the I/O voltage is up before the core voltage." To the best of my understanding, POC power will be on only during the period when the IO power supply is on and core power is off.

    My question is should I attach a pad to that cell and I have to manually add POC signal as in the attached pic(VDDPST is the I/O supply and VDD is the core supply)? Or the POC signal is created automatically?

    My second question is what is the difference of "internal macro" vs "core"? Is "internal macro" refers to analog circuits and "core" refers to digital portion?

    Thanks
    AllenClick image for larger version. 

Name:	Screenshot from 2019-03-17 00-01-21.png 
Views:	14 
Size:	42.1 KB 
ID:	151812

    •   AltAdvertisement

        
       

  2. #2
    Super Moderator
    Points: 52,113, Level: 55
    Achievements:
    7 years registered
    erikl's Avatar
    Join Date
    Sep 2008
    Location
    Germany
    Posts
    8,110
    Helped
    2682 / 2682
    Points
    52,113
    Level
    55

    Re: IC layout I/O design------power on control (POC) cell

    Quote Originally Posted by AllenD View Post
    My question is should I attach a pad to that cell and I have to manually add POC signal as in the attached pic(VDDPST is the I/O supply and VDD is the core supply)? Or the POC signal is created automatically?
    Depends. Maybe there's a pad cell available, which creates this signal (e.g. an LDO pad cell which creates the core Vdd from the pad Vddpst voltage. Its "power good" signal could be your POC). If not, you'll have to supply it from external.


    Quote Originally Posted by AllenD View Post
    My second question is what is the difference of "internal macro" vs "core"? Is "internal macro" refers to analog circuits and "core" refers to digital portion
    Usually an internal macro is understood as a complete RTL or high level language described, or even a compact layout core cell supplied by the foundry, whereas a core implementation is the (normally) not so compact solution created by the user (if the same application is compared). This is independent of digital or (mixed) analog.



    •   AltAdvertisement

        
       

  3. #3
    Advanced Member level 5
    Points: 9,197, Level: 22

    Join Date
    Apr 2016
    Posts
    1,917
    Helped
    338 / 338
    Points
    9,197
    Level
    22

    Re: IC layout I/O design------power on control (POC) cell

    #1. Usually some form of power control signal is routed through the entire IO ring, it doesn't come out of the chip through a pad. This is really weird. Read the documentation more carefully, I doubt you have to do anything other than adding this existing cell to the ring.

    #2. Sounds like usual TSMC gibberish. Those terms mean nothing without context. In the context of IO cells, I *think* they might be referring to periphery IO vs area IO. Again, TSMC is really good at creating these gibberish terms.
    Really, I am not Sam.



--[[ ]]--