I am designing a block named MDAC (multiplying DAC) which is an integral part of a pipelined ADC. now the basic functionality of the block is to find the difference of input and quantised data (i.e finding quantisation noise) and then amplify the same.

Obviously it is a fully differential structure. now I have to check the stability and transient response of the amplifier in actual working condition i.e connected with switched capacitor. Initially I'm using two clock phases, in the 1st phase it will be in sampling mode and in the second phase it will be in amplification mode. In the first phase I'm connecting the output directly to the input to define the input common mode of the amplifier. And in the second phase the feedback capacitor gets connected . Now the problem I'm facing in the second stage is that my biasing is totally destroyed and hence I'm getting very poor stability and transient response.

Please do suggest me a solution of how to develop the testbench to check the transient and stability analysis.

It's worth mentioning that I'm using Cadence Virtuoso for schematic editing and Spectre for simulation. It's a block of 100 MSPS 14bit pipelined ADC with 72dB gain and 1GHz UGF requirement