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  1. #1
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    Problem with simulation in Modelsim 10.5 of project verilog when adding module in vhd

    Greetings ... tell you that a couple of days ago I have been translating a verilog project to vhdl in Vivado 2017.3, I have managed to synthesize and implement this new vhdl project ... but I can not conclude correctly with the simulation in Modelsim 10.5, due to the next module.
    Code:
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;
    
    entity g1_wbus_stack_sm_vhdl is
        PORT (
                 i_clk              : IN std_logic;    
                 i_rst              : IN std_logic;    
                 i_fifos_almost_full: IN std_logic;    
                 i_rxff_empty       : IN std_logic;    
                 i_payload_done     : IN std_logic;    
                 o_wbus_wen         : OUT std_logic;    
                 o_hdr_en           : OUT std_logic;    
                 o_rxff_ren         : OUT std_logic;    
                 o_dw_select        : OUT std_logic_vector(2 DOWNTO 0));
                     
    end g1_wbus_stack_sm_vhdl;
    
    architecture Behavioral of g1_wbus_stack_sm_vhdl is
        type state_type is (Idle,Ren_Hdr,Hdr,Wbus_Wen,Wait4ffs,Ren);
        SIGNAL g1_wbus_stack_sm_sm      : state_type;	-- Current State ( Register )
        SIGNAL g1_wbus_stack_sm_next    : state_type;	-- Next State ( Combinatorial Bus )
        SIGNAL count_clr_l              : std_logic;	
        SIGNAL scount                   : std_logic_vector(2 DOWNTO 0);	
        SIGNAL ready_for_next           : std_logic;
    
    begin
    ------
        \sc_\ : entity work.slave_cntr generic map(3)
            PORT MAP (
                c   => i_clk,
                ar  => i_rst,
                ce  => count_clr_l,
                q   => scount);
    
    STATE_REG : process (i_clk,i_rst)
    begin
        if rising_edge(i_clk) then
            if (i_rst = '1') then
                g1_wbus_stack_sm_sm <= Idle;
            else
                g1_wbus_stack_sm_sm <= g1_wbus_stack_sm_next;
            end if;
        end if;
    end process;
    
    ready_for_next  <= NOT i_rxff_empty AND NOT i_fifos_almost_full;
    
    NEXT_STATE_COMB_LOGIC: process (g1_wbus_stack_sm_sm)  
        begin
            case (g1_wbus_stack_sm_sm) is
                    
            when Idle =>
                if ready_for_next = '1' then
                    g1_wbus_stack_sm_next <= Ren_Hdr;
                else
                    g1_wbus_stack_sm_next <= Idle;
                end if;
                
            when Ren_Hdr =>         
                      g1_wbus_stack_sm_next <= Hdr;
                
            when Hdr =>
                if  scount = "011" then 
                    g1_wbus_stack_sm_next <= Wbus_Wen;
                else
                    g1_wbus_stack_sm_next <= Hdr;
                end if;
                
            when Wbus_Wen =>    
                if  i_payload_done = '1' then
                    g1_wbus_stack_sm_next <= Idle;
                elsif scount = "111" and ready_for_next = '1' then
                    g1_wbus_stack_sm_next <= Ren;
                elsif scount = "111" then
                    g1_wbus_stack_sm_next <= Wait4ffs;
                else
                    g1_wbus_stack_sm_next <= Wbus_Wen;
                end if;
           
            when Wait4ffs =>
                if  ready_for_next = '1' then
                    g1_wbus_stack_sm_next <= Ren;
                else
                    g1_wbus_stack_sm_next <= Wait4ffs;
                end if;
                
            when Ren =>            
                g1_wbus_stack_sm_next <= Wbus_Wen;           
                
            when others =>
                
                g1_wbus_stack_sm_next <= Idle;                                               
            
               end case;       
    end process ;
        o_dw_select     <= scount;
    end Behavioral;
    The original code in verilog is as follows.

    Code:
    `timescale 100ps/100ps
    
    
    module g1_wbus_stack_sm (
    
      input              i_clk,                 // 
      input              i_rst,                 // 
    
      input              i_fifos_almost_full,   // Client fifos not ready
      input              i_rxff_empty,          // stack fifo empty
      input              i_payload_done,        // LENGTH DWs have been written
    
      output             o_wbus_wen,            // WBus Write enable
      output             o_hdr_en,              // Read first 256 bits incl. TLP header
      output             o_rxff_ren,            // Read stack fifo
    
      output [2:0]       o_dw_select            // Choose the outgoing Double Word
    
      );
    
    reg [7:0] g1_wbus_stack_sm_sm;    // Current State ( Register )
    reg [7:0] g1_wbus_stack_sm_next;  // Next State ( Combinatorial Bus )
    
    wire count_clr_l;   
    wire [2:0] scount;
    slave_cntr #(3) sc_( .c( i_clk  ), .ar( i_rst ), .ce( count_clr_l ), .q( scount ));
    
    parameter Idle               = 8'b0000_0000; //
    parameter Ren_Hdr            = 8'b0011_0001; //
    parameter Hdr                = 8'b0101_0010; //
    parameter Wbus_Wen           = 8'b1001_0011; //
    parameter Wait4ffs           = 8'b0000_0100; //
    parameter Ren                = 8'b0010_0101; //
    
    assign o_wbus_wen   = g1_wbus_stack_sm_sm[7];
    assign o_hdr_en     = g1_wbus_stack_sm_sm[6];
    assign o_rxff_ren   = g1_wbus_stack_sm_sm[5];
    assign count_clr_l  = g1_wbus_stack_sm_sm[4];
    
    always @(posedge i_clk or posedge i_rst)
      begin
         if( i_rst )
           g1_wbus_stack_sm_sm <= Idle;
         else
           g1_wbus_stack_sm_sm <= g1_wbus_stack_sm_next;
      end
    
    
    
    wire ready_for_next = ~i_rxff_empty & ~i_fifos_almost_full;
    
    always @(*)
    
      case ( g1_wbus_stack_sm_sm )
    
        Idle:
          if ( ready_for_next )
            g1_wbus_stack_sm_next = Ren_Hdr;
          else
            g1_wbus_stack_sm_next = Idle;
    
    
        Ren_Hdr:
          g1_wbus_stack_sm_next = Hdr;
    
        Hdr:
          if ( scount == 3'h3 )
            g1_wbus_stack_sm_next = Wbus_Wen;
          else
            g1_wbus_stack_sm_next = Hdr;
    
        Wbus_Wen:
          if ( i_payload_done )
            g1_wbus_stack_sm_next = Idle;
          else if ( (scount == 3'h7) & ready_for_next )
            g1_wbus_stack_sm_next = Ren;
          else if (scount == 3'h7)
            g1_wbus_stack_sm_next = Wait4ffs;
          else
            g1_wbus_stack_sm_next = Wbus_Wen;
    
        Wait4ffs:
          if ( ready_for_next )
            g1_wbus_stack_sm_next = Ren;
          else
            g1_wbus_stack_sm_next = Wait4ffs;
    
        Ren:
          g1_wbus_stack_sm_next = Wbus_Wen;
    
        default:
          g1_wbus_stack_sm_next = Idle;
    
      endcase
    
    assign o_dw_select = scount;
       
    endmodule
    The problem apparently is the initialization and the assignment of states to output signals of the module, but I'm not sure about that.
    Can someone please help me with this problem? In addition I leave attached the report of Modelsim of a correct simulation, and the one that I am obtaining when adding the vhdl module.

    - - - Updated - - -

    tell them that I have just added all the vhdl modules to the project, and I am having the following warnings in Modelsim and they all indicate the same warning.

    Code:
    # ** Warning: (vsim-8683) Uninitialized out port /stimulus/u_local_g1_test_bench/u_g1_top/U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_stack_vhdl/U_g1_wbus_stack_sm_vhdl/o_wbus_wen has no driver.
    # This port will contribute value (U) to the signal network.
    # ** Warning: (vsim-8683) Uninitialized out port /stimulus/u_local_g1_test_bench/u_g1_top/U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_stack_vhdl/U_g1_wbus_stack_sm_vhdl/o_hdr_en has no driver.
    # This port will contribute value (U) to the signal network.
    # ** Warning: (vsim-8683) Uninitialized out port /stimulus/u_local_g1_test_bench/u_g1_top/U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_stack_vhdl/U_g1_wbus_stack_sm_vhdl/o_rxff_ren has no driver.
    ...
    ...
    ...
    But this time the report ends in a failed result. I leave the full report attached.

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  2. #2
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    Re: Problem with simulation in Modelsim 10.5 of project verilog when adding module in

    The warnings are reasonable. The said outputs have no driver. The VHDL code is apparently incomplete, the respective assignments in Verilog code are missing.



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  3. #3
    Junior Member level 2
    Points: 133, Level: 1

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    Re: Problem with simulation in Modelsim 10.5 of project verilog when adding module in

    Thanks for replying to FvM ... I have managed to update my code based on an example that I found in the following way.

    Code:
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;
    
    entity g1_wbus_stack_sm_vhdl is  
        PORT (
                 i_clk              : IN std_logic;    
                 i_rst              : IN std_logic;    
                 i_fifos_almost_full: IN std_logic;    
                 i_rxff_empty       : IN std_logic;    
                 i_payload_done     : IN std_logic;    
                 o_wbus_wen         : OUT std_logic;    
                 o_hdr_en           : OUT std_logic;    
                 o_rxff_ren         : OUT std_logic;    
                 o_dw_select        : OUT std_logic_vector(2 DOWNTO 0));
                     
    end g1_wbus_stack_sm_vhdl;
    
    architecture Behavioral of g1_wbus_stack_sm_vhdl is
    
        CONSTANT Idle      : std_logic_vector(7 DOWNTO 0) := B"0000_0000";	
        CONSTANT Ren_Hdr   : std_logic_vector(7 DOWNTO 0) := B"0011_0001";    
        CONSTANT Hdr       : std_logic_vector(7 DOWNTO 0) := B"0101_0010";    
        CONSTANT Wbus_Wen  : std_logic_vector(7 DOWNTO 0) := B"1001_0011";    
        CONSTANT Wait4ffs  : std_logic_vector(7 DOWNTO 0) := B"0000_0100";    
        CONSTANT Ren       : std_logic_vector(7 DOWNTO 0) := B"0010_0101";
        
        SIGNAL g1_wbus_stack_sm_sm      : std_logic_vector(7 DOWNTO 0);	-- Current State ( Register )
        SIGNAL g1_wbus_stack_sm_next    : std_logic_vector(7 DOWNTO 0);	-- Next State ( Combinatorial Bus )
        SIGNAL count_clr_l              : std_logic;	
        SIGNAL scount                   : std_logic_vector(2 DOWNTO 0);	
        SIGNAL ready_for_next           : std_logic;
    
    begin
    
        \sc_\ : entity work.slave_cntr generic map(3)
            PORT MAP (
                c   => i_clk,
                ar  => i_rst,
                ce  => count_clr_l,
                q   => scount);
    
        o_wbus_wen  <= g1_wbus_stack_sm_sm(7);	
        o_hdr_en    <= g1_wbus_stack_sm_sm(6);	
        o_rxff_ren  <= g1_wbus_stack_sm_sm(5);	
        count_clr_l <= g1_wbus_stack_sm_sm(4);
        
    STATE_REG : process (i_clk,i_rst)
    begin
        if rising_edge (i_clk) then
            if (i_rst = '1') then
                g1_wbus_stack_sm_sm <= Idle;
            else
                g1_wbus_stack_sm_sm <= g1_wbus_stack_sm_next;
            end if;
        end if;
    end process;
    
    ready_for_next  <= (NOT i_rxff_empty) AND (NOT i_fifos_almost_full);
    
    NEXT_STATE_COMB_LOGIC: process (g1_wbus_stack_sm_sm,i_fifos_almost_full,i_rxff_empty,i_payload_done)  
        begin
            case g1_wbus_stack_sm_sm is
                    
            when Idle =>
                if ready_for_next = '1' then
                    g1_wbus_stack_sm_next <= Ren_Hdr;
                else
                    g1_wbus_stack_sm_next <= Idle;
                end if;
                
            when Ren_Hdr =>         
                      g1_wbus_stack_sm_next <= Hdr;
                
            when Hdr =>
                if  scount = "011" then 
                    g1_wbus_stack_sm_next <= Wbus_Wen;
                else
                    g1_wbus_stack_sm_next <= Hdr;
                end if;
                
            when Wbus_Wen =>    
                if  i_payload_done = '1' then
                    g1_wbus_stack_sm_next <= Idle;
                elsif scount = "111" and ready_for_next = '1' then
                    g1_wbus_stack_sm_next <= Ren;
                elsif scount = "111" then
                    g1_wbus_stack_sm_next <= Wait4ffs;
                else
                    g1_wbus_stack_sm_next <= Wbus_Wen;
                end if;
           
            when Wait4ffs =>
                if  ready_for_next = '1' then
                    g1_wbus_stack_sm_next <= Ren;
                else
                    g1_wbus_stack_sm_next <= Wait4ffs;
                end if;
                
            when Ren =>            
                g1_wbus_stack_sm_next <= Wbus_Wen;           
                
            when others =>
                
                g1_wbus_stack_sm_next <= Idle;                                               
            
               end case;       
    end process ;
        o_dw_select     <= scount;
    end Behavioral;
    In such a way that the initialization and the assignment that is seen in verilog is completed, but still I can not complete the simulation correctly and I get the following report that I leave attached.
    Code:
    # //  ModelSim SE-64 10.5 Feb 13 2016 
    # //
    # //  Copyright 1991-2016 Mentor Graphics Corporation
    # //  All Rights Reserved.
    # //
    # //  ModelSim SE-64 and its associated documentation contain trade
    # //  secrets and commercial or financial information that are the property of
    # //  Mentor Graphics Corporation and are privileged, confidential,
    # //  and exempt from disclosure under the Freedom of Information Act,
    # //  5 U.S.C. Section 552. Furthermore, this information
    # //  is prohibited from disclosure under the Trade Secrets Act,
    # //  18 U.S.C. Section 1905.
    # //
    # do {stimulus_simulate.do}
    # vsim -voptargs=""+acc"" -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.stimulus xil_defaultlib.glbl 
    # Start time: 15:44:13 on Mar 14,2019
    # ** Note: (vsim-3813) Design is being optimized due to module recompilation...
    # ** Note: (vopt-143) Recognized 1 FSM in architecture body "g1_sdma_engine_sm_vhdl(Behavioral)".
    # Loading sv_std.std
    # Loading work.sim_services_package(fast)
    # Loading work.stimulus(fast)
    # Loading work.local_g1_test_bench(fast)
    # Loading work.sim_rs485_top(fast)
    # Loading work.sim_rs485_pim(fast)
    # Loading work.sim_hotlink_ecl_top(fast)
    # Loading work.simulation_hotlink_stim(fast)
    # Loading work.g1_top(fast)
    # Loading work.g1_ipcat_lclk(fast)
    # Loading work.g1_ipcat_lclk_g1_ipcat_lclk_clk_wiz(fast)
    # Loading unisims_ver.BUFG(fast)
    # Loading unisims_ver.IBUF(fast)
    # Loading unisims_ver.MMCME2_ADV(fast)
    # Loading work.g1_core_ctrl_stat(fast)
    # Loading work.g1_user_regs_x16(fast)
    # Loading work.g1_ipcat_xadc(fast)
    # Loading unisims_ver.XADC(fast)
    # Loading work.g1_ipcat_sclk(fast)
    # Loading work.g1_ipcat_sclk_clk_wiz(fast)
    # Loading unisims_ver.IBUFDS(fast)
    # Loading unisims_ver.MMCME2_ADV(fast__1)
    # Loading unisims_ver.IDELAYCTRL(fast)
    # Loading work.g1_aurora_top(fast)
    # Loading work.g1_aurora(fast)
    # Loading work.g1_ipcat_aur_support(fast)
    # Loading work.g1_ipcat_aur_gt_common_wrapper(fast)
    # Loading unisims_ver.GTXE2_COMMON(fast)
    # Loading unisims_ver.IBUFDS_GTE2(fast)
    # Loading work.g1_ipcat_aur_CLOCK_MODULE(fast)
    # Loading unisims_ver.MMCME2_ADV(fast__2)
    # Loading work.g1_ipcat_aur_SUPPORT_RESET_LOGIC(fast)
    # Loading work.g1_ipcat_aur_rst_sync_exdes(fast)
    # Loading work.g1_ipcat_aur(fast)
    # Loading work.g1_ipcat_aur_core(fast)
    # Loading work.g1_ipcat_aur_RESET_LOGIC(fast)
    # Loading work.g1_ipcat_aur_rst_sync(fast)
    # Loading work.g1_ipcat_aur_AURORA_LANE(fast)
    # Loading work.g1_ipcat_aur_LANE_INIT_SM(fast)
    # Loading unisims_ver.SRLC32E(fast)
    # Loading unisims_ver.FDR(fast)
    # Loading unisims_ver.FDRE(fast)
    # Loading work.g1_ipcat_aur_cdc_sync(fast)
    # Loading work.g1_ipcat_aur_SYM_GEN(fast)
    # Loading work.g1_ipcat_aur_SYM_DEC(fast)
    # Loading work.g1_ipcat_aur_ERR_DETECT(fast)
    # Loading work.g1_ipcat_aur_WRAPPER(fast)
    # Loading unisims_ver.BUFGCE(fast)
    # Loading work.g1_ipcat_aur_cdc_sync(fast__1)
    # Loading work.g1_ipcat_aur_TX_STARTUP_FSM(fast)
    # Loading work.g1_ipcat_aur_rst_sync(fast__1)
    # Loading work.g1_ipcat_aur_RX_STARTUP_FSM(fast)
    # Loading work.g1_ipcat_aur_MULTI_GT(fast)
    # Loading work.G1_IPCAT_AUR_GTX(fast)
    # Loading unisims_ver.GTXE2_CHANNEL(fast)
    # Loading work.g1_ipcat_aur_common_reset_cbcc(fast)
    # Loading work.g1_ipcat_aur_rst_sync(fast__2)
    # Loading work.g1_ipcat_aur_rst_sync(fast__3)
    # Loading work.g1_ipcat_aur_common_logic_cbcc(fast)
    # Loading work.g1_ipcat_aur_SCRAMBLER_64B66B(fast)
    # Loading work.g1_ipcat_aur_cdc_sync(fast__2)
    # Loading work.g1_ipcat_aur_DESCRAMBLER_64B66B(fast)
    # Loading work.g1_ipcat_aur_BLOCK_SYNC_SM(fast)
    # Loading work.g1_ipcat_aur_CLOCK_CORRECTION_CHANNEL_BONDING(fast)
    # Loading work.g1_ipcat_aur_cdc_sync(fast__3)
    # Loading unisims_ver.FIFO36E1(fast)
    # Loading unisims_ver.FF36_INTERNAL_VLOG(fast)
    # Loading work.g1_ipcat_aur_CH_BOND_SLAVE(fast)
    # Loading work.g1_ipcat_aur_CLOCK_CORRECTION_CHANNEL_BONDING(fast__1)
    # Loading unisims_ver.FIFO36E1(fast__1)
    # Loading unisims_ver.FF36_INTERNAL_VLOG(fast__1)
    # Loading work.g1_ipcat_aur_CH_BOND_MASTER(fast)
    # Loading work.g1_ipcat_aur_AXI_TO_DRP(fast)
    # Loading work.g1_ipcat_aur_GLOBAL_LOGIC(fast)
    # Loading work.g1_ipcat_aur_CHANNEL_INIT_SM(fast)
    # Loading unisims_ver.FD(fast)
    # Loading unisims_ver.FDRE(fast__1)
    # Loading unisims_ver.FD(fast__1)
    # Loading work.g1_ipcat_aur_CHANNEL_BOND_GEN(fast)
    # Loading work.g1_ipcat_aur_CHANNEL_ERR_DETECT(fast)
    # Loading work.g1_ipcat_aur_AXI_TO_LL(fast)
    # Loading work.g1_ipcat_aur_AXI_TO_LL(fast__1)
    # Loading work.g1_ipcat_aur_TX_LL(fast)
    # Loading work.g1_ipcat_aur_TX_LL_DATAPATH(fast)
    # Loading work.g1_ipcat_aur_TX_LL_CONTROL_SM(fast)
    # Loading work.g1_ipcat_aur_LL_TO_AXI(fast)
    # Loading work.g1_ipcat_aur_RX_LL(fast)
    # Loading work.g1_ipcat_aur_RX_LL_DATAPATH(fast)
    # Loading work.g1_ipcat_aur_RX_LL_NFC(fast)
    # Loading work.g1_ipcat_aur_STANDARD_CC_MODULE(fast)
    # Loading work.g1_ipcat_aur_LL_TO_AXI(fast__1)
    # Loading work.g1_aur_rx_xoff_sm(fast)
    # Loading work.lbus_regs_x16(fast)
    # Loading unisims_ver.IBUFDS(fast__1)
    # Loading unisims_ver.OBUFDS(fast)
    # Loading work.g1_rs485_half_app_top(fast)
    # Loading work.g1_rs485_aur_rx_down(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_fifo_generator_v13_2_0(fast)
    # Loading unisims_ver.GND(fast)
    # Loading unisims_ver.VCC(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_fifo_generator_top(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_clk_x_pntrs(fast)
    # Loading unisims_ver.LUT4(fast__5)
    # Loading unisims_ver.LUT2(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_xpm_cdc_gray(fast)
    # Loading unisims_ver.LUT6(fast)
    # Loading unisims_ver.LUT3(fast__5)
    # Loading unisims_ver.LUT2(fast__2)
    # Loading unisims_ver.LUT4(fast__6)
    # Loading unisims_ver.LUT5(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_xpm_cdc_gray__1(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_rd_logic(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_rd_fwft(fast)
    # Loading unisims_ver.LUT4(fast__13)
    # Loading unisims_ver.FDSE(fast)
    # Loading unisims_ver.LUT4(fast__7)
    # Loading unisims_ver.LUT4(fast__9)
    # Loading unisims_ver.LUT3(fast__7)
    # Loading unisims_ver.LUT3(fast__2)
    # Loading unisims_ver.LUT4(fast__10)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_rd_status_flags_as(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_compare_1(fast)
    # Loading unisims_ver.CARRY4(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_compare_2(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_rd_bin_cntr(fast)
    # Loading unisims_ver.LUT1(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_wr_logic(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_wr_pf_as(fast)
    # Loading unisims_ver.FDSE(fast__1)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_wr_status_flags_as(fast)
    # Loading unisims_ver.LUT3(fast__10)
    # Loading unisims_ver.LUT2(fast__1)
    # Loading unisims_ver.LUT4(fast__15)
    # Loading unisims_ver.LUT4(fast__16)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_compare(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_compare_0(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_wr_bin_cntr(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_memory(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_mux__parameterized0(fast)
    # Loading unisims_ver.LUT3(fast__11)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper(fast)
    # Loading unisims_ver.RAMB18E1(fast__2)
    # Loading unisims_ver.RB18_INTERNAL_VLOG(fast__2)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized9(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized9(fast)
    # Loading unisims_ver.RAMB36E1(fast__3)
    # Loading unisims_ver.RB36_INTERNAL_VLOG(fast__3)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized10(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized10(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized11(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized11(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized12(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized12(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized13(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized13(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized14(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized14(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized15(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized15(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized16(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized16(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized17(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized17(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized18(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized18(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized0(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized0(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized19(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized19(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized20(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized20(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized21(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized21(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized22(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized22(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized23(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized23(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized24(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized24(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized25(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized25(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized26(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized26(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized27(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized27(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized28(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized28(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized1(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized1(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized29(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized29(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized30(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized30(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized31(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized31(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized32(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized32(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized33(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized33(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized34(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized34(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized35(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized35(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized36(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized36(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized37(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized37(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized38(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized38(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized2(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized2(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized39(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized39(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized40(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized40(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized41(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized41(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized42(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized42(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized43(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized43(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized44(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized44(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized45(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized45(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized46(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized46(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized47(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized47(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized48(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized48(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized3(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized3(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized49(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized49(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized50(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized50(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized51(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized51(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized52(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized52(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized53(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized53(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized54(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized54(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized55(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized55(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized56(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized56(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized57(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized57(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized58(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized58(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized4(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized4(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized59(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized59(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized60(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized60(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized61(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized61(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized62(fast)
    # Loading unisims_ver.SRL16E(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized62(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized63(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized63(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized5(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized5(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized6(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized6(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized7(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized7(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_width__parameterized8(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_blk_mem_gen_prim_wrapper__parameterized8(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_reset_blk_ramfifo(fast)
    # Loading unisims_ver.LUT2(fast__3)
    # Loading unisims_ver.LUT3(fast__8)
    # Loading unisims_ver.LUT4(fast__11)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_xpm_cdc_single(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_xpm_cdc_single__1(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_xpm_cdc_sync_rst(fast)
    # Loading work.g1_ipcat_aur_rx_dnld_fifo_xpm_cdc_sync_rst__1(fast)
    # Loading work.g1_rs485_aur_rx_sm(fast)
    # Loading work.g1_rs485_aur_tx_up(fast)
    # Loading work.g1_rs485_bin_lookup_ram(fast)
    # Loading work.g1_ipcat_bin_dpram(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_prim_wrapper(fast)
    # Loading unisims_ver.RAMB36E1(fast__4)
    # Loading unisims_ver.RB36_INTERNAL_VLOG(fast__4)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_prim_width__parameterized0(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_prim_wrapper__parameterized0(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_prim_width__parameterized1(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_prim_wrapper__parameterized1(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_prim_width__parameterized2(fast)
    # Loading work.g1_ipcat_bin_dpram_blk_mem_gen_prim_wrapper__parameterized2(fast)
    # Loading work.g1_tickin_tickout(fast)
    # Loading work.g1_ipcat_uclk(fast)
    # Loading work.g1_ipcat_uclk_g1_ipcat_uclk_clk_wiz(fast)
    # Loading unisims_ver.MMCME2_ADV(fast__3)
    # Loading work.g1_rs485_uart_set(fast)
    # Loading work.g1_rs485_uart(fast)
    # Loading work.g1_rs485_uart_sm(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_fifo_generator_v13_2_0(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_fifo_generator_top(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_clk_x_pntrs(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_xpm_cdc_gray(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_xpm_cdc_gray__1(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_rd_logic(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_rd_status_flags_as(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_compare_1(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_compare_2(fast)
    # Loading unisims_ver.LUT4(fast__12)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_rd_bin_cntr(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_wr_logic(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_wr_pf_as(fast)
    # Loading unisims_ver.LUT4(fast__17)
    # Loading unisims_ver.LUT4(fast__18)
    # Loading unisims_ver.LUT4(fast__19)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_wr_status_flags_as(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_compare(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_compare_0(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_wr_bin_cntr(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_memory(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_blk_mem_gen_prim_wrapper(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_reset_blk_ramfifo(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_xpm_cdc_single(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_xpm_cdc_single__1(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_xpm_cdc_sync_rst(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_prime_xpm_cdc_sync_rst__1(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_fifo_generator_v13_2_0(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_fifo_generator_top(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_rd_logic(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_dc_ss(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_updn_cntr(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_rd_status_flags_ss(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_compare_1(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_compare_2(fast)
    # Loading unisims_ver.LUT3(fast__12)
    # Loading unisims_ver.LUT4(fast)
    # Loading unisims_ver.LUT2(fast__4)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_rd_bin_cntr(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_wr_logic(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_wr_status_flags_ss(fast)
    # Loading unisims_ver.LUT4(fast__20)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_compare(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_compare_0(fast)
    # Loading unisims_ver.LUT1(fast__1)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_wr_bin_cntr(fast)
    # Loading unisims_ver.LUT4(fast__21)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_memory(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_blk_mem_gen_mux__parameterized0(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_blk_mem_gen_prim_wrapper(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_blk_mem_gen_prim_width__parameterized0(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_blk_mem_gen_prim_wrapper__parameterized0(fast)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_reset_blk_ramfifo(fast)
    # Loading unisims_ver.LUT3(fast__3)
    # Loading work.g1_ipcat_uart_tx_fifo_rs485_xpm_cdc_sync_rst(fast)
    # Loading unisims_ver.LUT4(fast__4)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_fifo_generator_v13_2_0(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_fifo_generator_top(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_clk_x_pntrs(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_xpm_cdc_gray(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_xpm_cdc_gray__1(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_rd_logic(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_rd_status_flags_as(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_compare_1(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_compare_2(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_rd_bin_cntr(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_wr_logic(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_wr_status_flags_as(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_compare(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_compare_0(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_wr_bin_cntr(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_memory(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_blk_mem_gen_mux__parameterized0(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_blk_mem_gen_prim_wrapper(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_blk_mem_gen_prim_width__parameterized0(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_blk_mem_gen_prim_wrapper__parameterized0(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_reset_blk_ramfifo(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_xpm_cdc_single(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_xpm_cdc_single__1(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_xpm_cdc_sync_rst(fast)
    # Loading work.g1_ipcat_uart_rx_fifo_rs485_xpm_cdc_sync_rst__1(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_fifo_generator_v13_2_0(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_fifo_generator_top(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_clk_x_pntrs(fast)
    # Loading unisims_ver.LUT4(fast__2)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_xpm_cdc_gray(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_xpm_cdc_gray__1(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_rd_logic(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_rd_status_flags_as(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_rd_bin_cntr(fast)
    # Loading unisims_ver.LUT3(fast__1)
    # Loading unisims_ver.LUT4(fast__1)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_wr_logic(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_wr_status_flags_as(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_wr_bin_cntr(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_memory(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_blk_mem_gen_prim_wrapper(fast)
    # Loading unisims_ver.RAMB18E1(fast__3)
    # Loading unisims_ver.RB18_INTERNAL_VLOG(fast__3)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_reset_blk_ramfifo(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_xpm_cdc_single(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_xpm_cdc_single__1(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_xpm_cdc_sync_rst(fast)
    # Loading work.g1_ipcat_upload_q_fifo_rs485_xpm_cdc_sync_rst__1(fast)
    # Loading work.g1_rs485_uart_upld(fast)
    # Loading work.g1_ipcat_uart16550_rs485(fast)
    # Loading work.g1_ipcat_uart16550_rs485_axi_uart16550(fast)
    # Loading work.g1_ipcat_uart16550_rs485_axi_lite_ipif(fast)
    # Loading work.g1_ipcat_uart16550_rs485_slave_attachment(fast)
    # Loading work.g1_ipcat_uart16550_rs485_address_decoder(fast)
    # Loading unisims_ver.LUT2(fast__5)
    # Loading unisims_ver.LUT3(fast__13)
    # Loading unisims_ver.LUT4(fast__22)
    # Loading work.g1_ipcat_uart16550_rs485_xuart(fast)
    # Loading work.g1_ipcat_uart16550_rs485_ipic_if(fast)
    # Loading work.g1_ipcat_uart16550_rs485_uart16550(fast)
    # Loading unisims_ver.LUT2(fast__6)
    # Loading unisims_ver.LUT4(fast__23)
    # Loading unisims_ver.LUT4(fast__24)
    # Loading unisims_ver.LUT3(fast__6)
    # Loading unisims_ver.LUT3(fast__14)
    # Loading unisims_ver.LUT4(fast__25)
    # Loading unisims_ver.LUT3(fast__15)
    # Loading unisims_ver.LUT4(fast__26)
    # Loading unisims_ver.LUT3(fast__16)
    # Loading work.g1_ipcat_uart16550_rs485_rx_fifo_block(fast)
    # Loading work.g1_ipcat_uart16550_rs485_rx_fifo_control(fast)
    # Loading unisims_ver.LUT3(fast__9)
    # Loading unisims_ver.LUT4(fast__27)
    # Loading unisims_ver.LUT3(fast)
    # Loading unisims_ver.LUT4(fast__28)
    # Loading unisims_ver.LUT3(fast__17)
    # Loading unisims_ver.LUT2(fast__7)
    # Loading unisims_ver.LUT4(fast__29)
    # Loading work.g1_ipcat_uart16550_rs485_srl_fifo_rbu_f__parameterized0(fast)
    # Loading work.g1_ipcat_uart16550_rs485_cntr_incr_decr_addn_f_0(fast)
    # Loading unisims_ver.LUT4(fast__30)
    # Loading unisims_ver.LUT2(fast__8)
    # Loading work.g1_ipcat_uart16550_rs485_dynshreg_f__parameterized0(fast)
    # Loading unisims_ver.LUT4(fast__31)
    # Loading work.g1_ipcat_uart16550_rs485_tx_fifo_block(fast)
    # Loading work.g1_ipcat_uart16550_rs485_srl_fifo_rbu_f(fast)
    # Loading work.g1_ipcat_uart16550_rs485_cntr_incr_decr_addn_f(fast)
    # Loading unisims_ver.LUT3(fast__18)
    # Loading work.g1_ipcat_uart16550_rs485_dynshreg_f(fast)
    # Loading unisims_ver.ODDR(fast)
    # Loading unisims_ver.LUT4(fast__32)
    # Loading unisims_ver.LUT4(fast__33)
    # Loading unisims_ver.LUT4(fast__3)
    # Loading unisims_ver.LUT3(fast__19)
    # Loading work.g1_ipcat_uart16550_rs485_rx16550(fast)
    # Loading unisims_ver.LUT4(fast__34)
    # Loading unisims_ver.LUT4(fast__35)
    # Loading unisims_ver.MUXF7(fast)
    # Loading unisims_ver.LUT4(fast__36)
    # Loading unisims_ver.LUT4(fast__37)
    # Loading unisims_ver.LUT4(fast__38)
    # Loading unisims_ver.LUT4(fast__39)
    # Loading unisims_ver.LUT3(fast__20)
    # Loading unisims_ver.LUT4(fast__40)
    # Loading unisims_ver.LUT3(fast__21)
    # Loading unisims_ver.LUT3(fast__22)
    # Loading unisims_ver.LUT3(fast__4)
    # Loading unisims_ver.LUT4(fast__41)
    # Loading unisims_ver.LUT4(fast__42)
    # Loading unisims_ver.LUT4(fast__43)
    # Loading unisims_ver.LUT4(fast__44)
    # Loading unisims_ver.LUT3(fast__23)
    # Loading work.g1_ipcat_uart16550_rs485_tx16550(fast)
    # Loading unisims_ver.LUT4(fast__45)
    # Loading unisims_ver.LUT4(fast__46)
    # Loading unisims_ver.LUT4(fast__47)
    # Loading unisims_ver.LUT3(fast__24)
    # Loading unisims_ver.LUT3(fast__25)
    # Loading unisims_ver.LUT3(fast__26)
    # Loading work.g1_ipcat_uart16550_rs485_xuart_tx_load_sm(fast)
    # Loading unisims_ver.LUT3(fast__27)
    # Loading unisims_ver.LUT3(fast__28)
    # Loading unisims_ver.LUT3(fast__29)
    # Loading unisims_ver.LUT3(fast__30)
    # Loading unisims_ver.LUT3(fast__31)
    # Loading unisims_ver.LUT4(fast__48)
    # Loading unisims_ver.LUT3(fast__32)
    # Loading unisims_ver.OBUFTDS(fast)
    # Loading work.g1_ptiq_interface(fast)
    # Loading unisims_ver.PULLUP(fast)
    # Loading work.simulation_aurora_xactor_g1(fast)
    # Loading work.g1_aurora(fast__1)
    # Loading work.simulation_aurora_tx_g1(fast)
    # Loading work.simulation_aurora_rx_g1(fast)
    # Loading work.l3_local_bus_model(fast)
    # Loading work.l3_ptiq_serial_in(fast)
    # Loading work.glbl(fast)
    # Loading std.standard
    # Loading std.textio(body)
    # Loading ieee.std_logic_1164(body)
    # Loading work.red(behave)#1
    # Loading work.dreg_clr(behave)#1
    # Loading work.dreg_clr(behave)#2
    # Loading work.dreg_clr(behave)#3
    # Loading synopsys.attributes
    # Loading ieee.std_logic_misc(body)
    # Loading work.siso_sr(behave)#1
    # Loading work.dreg_clr(behave)#4
    # Loading work.puls_exp(behave)#1
    # Loading work.siso_sr(behave)#2
    # Loading work.dreg_clr(behave)#5
    # Loading work.dreg_clr_pre(behave)#1
    # Loading work.scflag(behave)#1
    # Loading work.dreg_clr(behave)#6
    # Loading work.dreg_clr(behave)#7
    # Loading work.siso_sr(behave)#3
    # Loading work.siso_sr(behave)#4
    # Loading ieee.std_logic_arith(body)
    # Loading ieee.std_logic_unsigned(body)
    # Loading work.upcntr(behave)#1
    # Loading ieee.numeric_std(body)
    # Loading work.g1_hotlink_half_app_top_vhdl(behavioral)#1
    # Loading work.upcntr(behave)#2
    # Loading work.g1_asa_top_vhdl(behavioral)#1
    # Loading work.g1_wbus_top_vhdl(behavioral)#1
    # Loading work.g1_wbus_stack_vhdl(behavioral)#1
    # Loading work.dreg_clr(behave)#8
    # Loading work.g1_ipcat_wbus_rx_fifo(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_fifo_generator_v13_2_0(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_fifo_generator_top(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_rd_logic(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_dc_ss(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_updn_cntr(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_rd_status_flags_ss(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_rd_bin_cntr(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_wr_logic(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_wr_status_flags_ss(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_wr_bin_cntr(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_memory(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_prim_wrapper(fast)
    # Loading unisims_ver.RAMB36E1(fast)
    # Loading unisims_ver.RB36_INTERNAL_VLOG(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_prim_width__parameterized0(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_prim_wrapper__parameterized0(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_prim_width__parameterized1(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_prim_wrapper__parameterized1(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_prim_width__parameterized2(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_blk_mem_gen_prim_wrapper__parameterized2(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_reset_blk_ramfifo(fast)
    # Loading work.g1_ipcat_wbus_rx_fifo_xpm_cdc_sync_rst(fast)
    # Loading work.dreg_clr(behave)#9
    # Loading work.preload_upcntr(behave)#1
    # Loading work.upcntr(behave)#3
    # Loading work.g1_wbus_stack_sm_vhdl(behavioral)#1
    # Loading work.slave_cntr(behave)#1
    # Loading work.g1_wbus_client_fifos_vhdl(behavioral)#1
    # Loading work.g1_ipcat_wbus_client_fifo(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_fifo_generator_v13_2_0(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_fifo_generator_top(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_clk_x_pntrs(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_xpm_cdc_gray(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_xpm_cdc_gray__1(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_rd_logic(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_rd_fwft(fast)
    # Loading unisims_ver.LUT4(fast__8)
    # Loading work.g1_ipcat_wbus_client_fifo_rd_dc_fwft_ext_as(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_rd_status_flags_as(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_compare_1(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_compare_2(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_rd_bin_cntr(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_wr_logic(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_wr_dc_fwft_ext_as(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_wr_status_flags_as(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_compare(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_compare_0(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_wr_bin_cntr(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_memory(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_blk_mem_gen_prim_wrapper(fast)
    # Loading unisims_ver.RAMB36E1(fast__1)
    # Loading unisims_ver.RB36_INTERNAL_VLOG(fast__1)
    # Loading work.g1_ipcat_wbus_client_fifo_reset_blk_ramfifo(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_xpm_cdc_single(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_xpm_cdc_single__1(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_xpm_cdc_sync_rst(fast)
    # Loading work.g1_ipcat_wbus_client_fifo_xpm_cdc_sync_rst__1(fast)
    # Loading work.g1_sdma_top_vhdl(behavioral)#1
    # Loading work.g1_sdma_engine_vhdl(behavioral)#1
    # Loading work.lbus_regs_x16_vhdl(behavioral)#1
    # Loading work.lbus_regs_x16_vhdl(behavioral)#2
    # Loading work.dreg_clr(behave)#11
    # Loading work.dreg_clr(behave)#12
    # Loading work.dreg_clr(behave)#10
    # Loading work.g1_sdma_engine_sm_vhdl(behavioral)#1
    # Loading work.slave_cntr(behave)#3
    # Loading work.g1_sdma_tlp_header_vhdl(behavioral)#1
    # Loading work.fed(behave)#1
    # Loading work.g1_sdma_32_port_arb_vhdl(behavioral)#1
    # Loading work.g1_rr_arb_x16_vhdl(behavioral)#1
    # Loading work.g1_rr_arb_x4_vhdl(behavioral)#1
    # Loading work.g1_rr_arb_x4_sm_vhdl(behavioral)#1
    # Loading work.g1_sdma2aurora_vhdl(behavioral)#1
    # Loading work.upcntr(behave)#4
    # Loading work.upcntr(behave)#5
    # Loading work.g1_ipcat_s2a_fifo(fast)
    # Loading work.g1_ipcat_s2a_fifo_fifo_generator_v13_2_0(fast)
    # Loading work.g1_ipcat_s2a_fifo_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_s2a_fifo_fifo_generator_top(fast)
    # Loading work.g1_ipcat_s2a_fifo_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_s2a_fifo_clk_x_pntrs(fast)
    # Loading work.g1_ipcat_s2a_fifo_xpm_cdc_gray(fast)
    # Loading work.g1_ipcat_s2a_fifo_xpm_cdc_gray__1(fast)
    # Loading work.g1_ipcat_s2a_fifo_rd_logic(fast)
    # Loading work.g1_ipcat_s2a_fifo_rd_fwft(fast)
    # Loading work.g1_ipcat_s2a_fifo_rd_status_flags_as(fast)
    # Loading work.g1_ipcat_s2a_fifo_compare_1(fast)
    # Loading work.g1_ipcat_s2a_fifo_compare_2(fast)
    # Loading work.g1_ipcat_s2a_fifo_rd_bin_cntr(fast)
    # Loading work.g1_ipcat_s2a_fifo_wr_logic(fast)
    # Loading work.g1_ipcat_s2a_fifo_wr_dc_as(fast)
    # Loading work.g1_ipcat_s2a_fifo_wr_status_flags_as(fast)
    # Loading work.g1_ipcat_s2a_fifo_compare(fast)
    # Loading work.g1_ipcat_s2a_fifo_compare_0(fast)
    # Loading work.g1_ipcat_s2a_fifo_wr_bin_cntr(fast)
    # Loading work.g1_ipcat_s2a_fifo_memory(fast)
    # Loading work.g1_ipcat_s2a_fifo_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_s2a_fifo_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_s2a_fifo_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_s2a_fifo_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_s2a_fifo_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_s2a_fifo_blk_mem_gen_prim_wrapper(fast)
    # Loading unisims_ver.RAMB36E1(fast__2)
    # Loading unisims_ver.RB36_INTERNAL_VLOG(fast__2)
    # Loading work.g1_ipcat_s2a_fifo_reset_blk_ramfifo(fast)
    # Loading work.g1_ipcat_s2a_fifo_xpm_cdc_single(fast)
    # Loading work.g1_ipcat_s2a_fifo_xpm_cdc_single__1(fast)
    # Loading work.g1_ipcat_s2a_fifo_xpm_cdc_sync_rst(fast)
    # Loading work.g1_ipcat_s2a_fifo_xpm_cdc_sync_rst__1(fast)
    # Loading work.g1_sdma2aurora_sm_vhdl(behavioral)#1
    # Loading work.slave_cntr(behave)#2
    # Loading work.g1_widemux_32_x_16bit_vhdl(behavioral)#1
    # Loading work.g1_mux_stage_4x1_vhdl(behavioral)#1
    # Loading work.g1_mux_stage_4x1_vhdl(behavioral)#2
    # Loading work.g1_mux_stage_4x1_vhdl(behavioral)#3
    # Loading work.g1_applic_top_vhdl(behavioral)#1
    # Loading work.g1_local_bus_interface_example_vhdl(behavioral)#1
    # Loading work.g1_ipcat_example_fifo(fast)
    # Loading work.g1_ipcat_example_fifo_fifo_generator_v13_2_0(fast)
    # Loading work.g1_ipcat_example_fifo_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_example_fifo_fifo_generator_top(fast)
    # Loading work.g1_ipcat_example_fifo_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_example_fifo_clk_x_pntrs(fast)
    # Loading work.g1_ipcat_example_fifo_xpm_cdc_gray(fast)
    # Loading work.g1_ipcat_example_fifo_xpm_cdc_gray__1(fast)
    # Loading work.g1_ipcat_example_fifo_rd_logic(fast)
    # Loading work.g1_ipcat_example_fifo_rd_status_flags_as(fast)
    # Loading work.g1_ipcat_example_fifo_compare_1(fast)
    # Loading work.g1_ipcat_example_fifo_compare_2(fast)
    # Loading work.g1_ipcat_example_fifo_rd_bin_cntr(fast)
    # Loading work.g1_ipcat_example_fifo_wr_logic(fast)
    # Loading work.g1_ipcat_example_fifo_wr_status_flags_as(fast)
    # Loading work.g1_ipcat_example_fifo_compare(fast)
    # Loading work.g1_ipcat_example_fifo_compare_0(fast)
    # Loading work.g1_ipcat_example_fifo_wr_bin_cntr(fast)
    # Loading work.g1_ipcat_example_fifo_memory(fast)
    # Loading work.g1_ipcat_example_fifo_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_example_fifo_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_example_fifo_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_example_fifo_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_example_fifo_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_example_fifo_blk_mem_gen_prim_wrapper(fast)
    # Loading unisims_ver.RAMB18E1(fast)
    # Loading unisims_ver.RB18_INTERNAL_VLOG(fast)
    # Loading work.g1_ipcat_example_fifo_reset_blk_ramfifo(fast)
    # Loading work.g1_ipcat_example_fifo_xpm_cdc_single(fast)
    # Loading work.g1_ipcat_example_fifo_xpm_cdc_single__1(fast)
    # Loading work.g1_ipcat_example_fifo_xpm_cdc_sync_rst(fast)
    # Loading work.g1_ipcat_example_fifo_xpm_cdc_sync_rst__1(fast)
    # Loading work.dreg_clr(behave)#13
    # Loading work.g1_hotlink_init_vhdl(behavioral)#1
    # Loading work.siso_sr(behave)#5
    # Loading work.upcntr(behave)#6
    # Loading work.sipo_left_shift_sr(behave)#1
    # Loading work.g1_hotlink_top_vhdl(behavioral)#1
    # Loading work.lbus_regs_x16_vhdl(behavioral)#3
    # Loading work.lbus_regs_x16_vhdl(behavioral)#4
    # Loading work.lbus_regs_x16_vhdl(behavioral)#5
    # Loading work.g1_hotlink_rx_vhdl(behavioral)#1
    # Loading work.g1_enable_sm_vhdl(behavioral)#1
    # Loading work.dreg_clr_sclear(behave)#1
    # Loading work.g1_ipcat_sdma_18kbit_sfifo(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_fifo_generator_v13_2_0(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_fifo_generator_v13_2_0_synth(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_fifo_generator_top(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_fifo_generator_ramfifo(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_rd_logic(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_dc_ss_fwft(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_updn_cntr(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_rd_fwft(fast)
    # Loading unisims_ver.LUT4(fast__14)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_rd_status_flags_ss(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_compare_1(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_compare_2(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_rd_bin_cntr(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_wr_logic(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_wr_status_flags_ss(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_compare(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_compare_0(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_wr_bin_cntr(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_memory(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_blk_mem_gen_v8_4_0(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_blk_mem_gen_v8_4_0_synth(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_blk_mem_gen_top(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_blk_mem_gen_generic_cstr(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_blk_mem_gen_prim_width(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_blk_mem_gen_prim_wrapper(fast)
    # Loading unisims_ver.RAMB18E1(fast__1)
    # Loading unisims_ver.RB18_INTERNAL_VLOG(fast__1)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_reset_blk_ramfifo(fast)
    # Loading work.g1_ipcat_sdma_18kbit_sfifo_xpm_cdc_sync_rst(fast)
    # Loading work.g1_hotlink_rx_sm_vhdl(behavioral)#1
    # Loading work.upcntr(behave)#8
    # Loading work.dreg_clr(behave)#14
    # Loading work.g1_hotlink_tx_vhdl(behavioral)#1
    # Loading work.g1_hotlink_tx_unit_vhdl(behavioral)#1
    # Loading work.dreg_clr(behave)#15
    # Loading work.dreg_clr(behave)#16
    # Loading work.dreg_clr(behave)#17
    # Loading work.dreg_clr(behave)#18
    # Loading work.upcntr(behave)#9
    # Loading work.preload_dwncntr(behave)#1
    # Loading work.g1_hotlink_tx_sm_vhdl(behavioral)#1
    # Loading work.dreg_clr(behave)#19
    # Loading work.upcntr(behave)#10
    # Loading work.upcntr(behave)#11
    # Loading work.g1_hotlink_pim_vhdl(behavioral)#1
    # Loading work.upcntr(behave)#7
    # Loading ieee.vital_timing(body)
    # Loading ieee.vital_primitives(body)
    # Loading unisim.vpkg(body)
    # Loading unisim.oddr(oddr_v)#1
    # Loading unisim.oserdese2(oserdese2_v)#1
    # Loading secureip.OSERDESE2_WRAP(fast)
    # Loading secureip.B_OSERDESE2(fast)
    # Loading unisim.odelaye2(odelaye2_v)#1
    # Loading unisim.oserdese2(oserdese2_v)#2
    # Loading secureip.OSERDESE2_WRAP(fast__1)
    # Loading secureip.B_OSERDESE2(fast__1)
    # Loading work.g1_aurora_arb_sm(fast)
    # Loading unisim.ibufds(ibufds_v)#1
    # Loading unisim.obuftds(obuftds_v)#1
    # Loading work.upcntr(behave)#12
    # Loading work.dreg_clr_sclear(behave)#2
    # Loading work.puls_exp(behave)#2
    # Loading work.sipo_left_shift_sr(behave)#2
    # Loading work.sipo_left_shift_sr(behave)#3
    # Loading work.puls_exp(behave)#3
    # Loading work.puls_exp(behave)#4
    # Loading work.puls_exp(behave)#5
    # Loading work.sipo_left_shift_sr(behave)#4
    # Loading work.upcntr(behave)#13
    # Loading work.preload_dwncntr(behave)#2
    # Loading work.preload_upcntr(behave)#2
    # 1
    # 1
    # .main_pane.wave.interior.cs.body.pw.wf
    # .main_pane.structure.interior.cs.body.struct
    # .main_pane.objects.interior.cs.body.tree
    # ---------------------------------------------------------------------------------------
    # Test Name        : wtest_hotlink_pim1_tx_simple
    # 
    # Test Description : Host sends wbus-based tx messages and verifies tx stats.
    # ---------------------------------------------------------------------------------------
    # Aurora Tx Model: Channel is Down.
    # Reading ebc Bus commands from "C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4_02_IEA/fpgas/g1/local_sim/tests/wtest_hotlink_pim1_tx_simple/ebc.ini".
    # ebc (  0): Delaying 100 clock cycles.                                                                                                      
    # Warning: [Unisim MMCME2_ADV-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance stimulus.u_local_g1_test_bench.u_g1_top.U_pim0.u_g1_ipcat_uclk1.inst.mmcm_adv_inst 
    # Warning: [Unisim MMCME2_ADV-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance stimulus.u_local_g1_test_bench.u_g1_top.U_pim0.u_g1_ipcat_uclk2.inst.mmcm_adv_inst 
    # Warning: [Unisim MMCME2_ADV-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance stimulus.u_local_g1_test_bench.u_g1_top.U_pim0.u_g1_ipcat_uclk3.inst.mmcm_adv_inst 
    # =========================================================================
    # Starting Reset Procedure                                                                                                        
    # =========================================================================
    # ebc (  1): Delaying 150 clock cycles.                                                                                                      
    # ebc (  2): Write RW_G1_MMCM_EN: I@                                                                                                         
    #                          ebc Write, cs/Addr/Data = cs0 0x0000c 0x0001
    # ebc (  3): Read W Poll RO_G1_MMCM_STAT: I@ Wait for clocks locked.                                                                         
    #                          ebc Poll, cs/Addr/Exp/Actual = cs0 0x0000e 0x0003 0x0002
    #                          ebc Poll, cs/Addr/Exp/Actual = cs0 0x0000e 0x0003 0x0003
    # ebc (  4): Delaying 400 clock cycles.                                                                                                      
    # ebc (  5): Write RW_G1_TIMESTAMP_CONTROL: I@ Enable the timestamp counter                                                                  
    #                          ebc Write, cs/Addr/Data = cs0 0x00016 0x0001
    # ebc (  6): Read W Mask & Verify RO_G1_CONSTANT: I@ Verify L1 Constant                                                                      
    #                          ebc Read, cs/Addr/Exp/Actual = cs0 0x00000 0x4701 0x4701
    # ebc (  7): Write RW_G1_APP_CTRL + 262144: I@ Configure Hotlink Tx Period                                                                   
    # //!
    # //!
    # //!
    # //!
    # //! ^^^^^^^ ERROR! EBC transaction timeout waiting for TRANSFER_ACK.
    # //!
    # //!
    # //!
    # //!
    # Aurora Tx Model: Channel is Up.
    # Aurora Tx Model: Read to Stream.
    # Aurora Tx Model: Tx Stream contains (5) Packets
    # Aurora Tx Model: Writing Tx 256-bit Word (0x60000010_01a000ff_00000000_00000000_0x01020304_05060708_090a0b0c_0d0e0f10).
    # Aurora Tx Model: Writing Tx 256-bit Word (0x11121314_15161718_191a1b1c_1d1e1f20_0x21222324_25262728_292a2b2c_2d2e2f30).
    # Aurora Tx Model: Writing Tx 256-bit Word (0x31323334_35363738_393a3b3c_3d3e3f40_0xfeedbeef_feedbeef_feedbeef_feedbeef).
    # Aurora Tx Model: Sent (1) TLP's: TCF Writes Unrelated  64-byte packet to EP at DDR2 address 0x00000000.                                        
    # Aurora Tx Model: Writing Tx 256-bit Word (0x60000006_01a000ff_80000000_00420000_0x80000000_00000010_01020304_05060708).
    # Aurora Tx Model: Writing Tx 256-bit Word (0x090a0b0c_0d0e0f10_feedbeef_feedbeef_0xfeedbeef_feedbeef_feedbeef_feedbeef).
    # Aurora Tx Model: Sent (2) TLP's: TCF Writes  24-byte packet to EP at DDR2 address 0x8000000000420000.                                          
    # Aurora Tx Model: Writing Tx 256-bit Word (0x60000006_01a000ff_80000000_00420000_0x80000000_00000010_11121314_15161718).
    # Aurora Tx Model: Writing Tx 256-bit Word (0x191a1b1c_1d1e1f20_feedbeef_feedbeef_0xfeedbeef_feedbeef_feedbeef_feedbeef).
    # Aurora Tx Model: Sent (3) TLP's: TCF Writes  24-byte packet to EP at DDR2 address 0x8000000000420000.                                          
    # Aurora Tx Model: Writing Tx 256-bit Word (0x60000006_01a000ff_80000000_00420000_0x80000000_00000010_21222324_25262728).
    # Aurora Tx Model: Writing Tx 256-bit Word (0x292a2b2c_2d2e2f30_feedbeef_feedbeef_0xfeedbeef_feedbeef_feedbeef_feedbeef).
    # Aurora Tx Model: Sent (4) TLP's: TCF Writes  24-byte packet to EP at DDR2 address 0x8000000000420000.                                          
    # Aurora Tx Model: Writing Tx 256-bit Word (0x60000006_01a000ff_80000000_00420000_0x80000000_00000010_31323334_35363738).
    # Aurora Tx Model: Writing Tx 256-bit Word (0x393a3b3c_3d3e3f40_feedbeef_feedbeef_0xfeedbeef_feedbeef_feedbeef_feedbeef).
    # Aurora Tx Model: Sent (5) TLP's: TCF Writes  24-byte packet to EP at DDR2 address 0x8000000000420000.                                          
    # Aurora Tx Model: Tx Stream finished.
    # ---------------------------------------------------------------------------------------
    # Test Name: wtest_hotlink_pim1_tx_simple
    # 
    #                            Attempts   Failures      
    # Host Read Verifies :          1          0
    # User Verifies      :          6          1
    # 
    # Result             : ** FAILED! **
    # ---------------------------------------------------------------------------------------
    # ** Note: $finish    : ../../../../RsApp.srcs/sim_1/imports/src/stimulus.sv(134)
    #    Time: 51754291 ps  Iteration: 0  Instance: /stimulus
    # //! Note: simulation ended at 51.8 uS, 41.4 percent of the fail-safe timeout.
    # //! ---------------------------------------------------------------------------------------
    # End time: 15:53:38 on Mar 14,2019, Elapsed time: 0:09:25
    # Errors: 0, Warnings: 0
    Last edited by ads-ee; 15th March 2019 at 16:06. Reason: added contents of rar file



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  4. #4
    Super Moderator
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    Re: Problem with simulation in Modelsim 10.5 of project verilog when adding module in

    Your simulation is loading and running. You have a design error in one or more the files in the design.

    Find the statement that generates the "ERROR! EBC transaction timeout waiting for TRANSFER_ACK" in the code and trace what generates that back through the simulation, until you find out what code doesn't generate the acknowledge.

    I doubt anyone can tell you where to look as you would have to supply all the code and the testbench and then we would be doing your job to debug this. Learn to trace signals back through your code to find the problem, put the signals that generate outputs in the wave window to see how outputs aren't being generated properly and keep tracing back from there.



  5. #5
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    Re: Problem with simulation in Modelsim 10.5 of project verilog when adding module in

    greetings ads-ee ... after many simulation tests, without any good results, I tell you that I have managed to find the problem in my project.
    As I had mentioned before, I have been translating a verilog project into vhdl, but I did not mention that I only translated part of the project (because it was really what I was interested in translating), in this translated part of my project, many of the modules use a library g1_partslib_pkg.vhd which is a vhdl equivalent of g1_partslib.v which is used by the part that is still in verilog (that seems according to the hierarchy that is shown in the attached image)

    Click image for larger version. 

Name:	vivado_hierarchy.png 
Views:	3 
Size:	98.8 KB 
ID:	151878

    But in the simulation herarchy indicates that only g1_partslib_pkg.vhd is being used in the whole project (as shown in the attached image),

    Click image for larger version. 

Name:	modelsim_hierarchy.PNG 
Views:	1 
Size:	130.0 KB 
ID:	151879

    To verify this only added vhdl modules that do not use the library g1_partslib_pkg.vhd, with this change the simulation concluded correctly.
    Now my question is why Modelsim makes use of the library g1_partslib_pkg.vhd in the part that is in verilog, is there any way to configure this?
    Any help is welcome, thanks in advance.



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  6. #6
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    Re: Problem with simulation in Modelsim 10.5 of project verilog when adding module in

    If the name of the module and the name of the entity are the same for that library then Modelsim will use the VHDL version only.

    I don't know if this is what is happening, since all you've supplied is useless pictures of file names with no way determine the content of those files.



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