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[SOLVED] ERROR Vivado: [DRC MDRV-1] Multiple Driver Nets: Net has multiple drivers

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Cesar0182

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Greetings ... comment I am trying to implement a project with vivado 2017.3 from a tcl script, but unfortunately one module is generating the following error.
Code:
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[9].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout[9] has multiple drivers: U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[3].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[0].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[1].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[2].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[7].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[5].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[4].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[6].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[8].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[10].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[9].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[12].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[11].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[15].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q, U_pim1_vhdl/U_g1_asa_top_vhdl/U_g1_wbus_top_vhdl/U_g1_wbus_client_fifos_vhdl/u_client[14].U_client_ff/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_bm.dout_i_reg[9]/Q... and (the first 15 of 26 listed).
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port io_g1_tp[0] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port io_g1_tp[1] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port io_g1_tp[2] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port io_g1_tp[3] expects both input and output buffering but the buffers are incomplete.
INFO: [Project 1-461] DRC finished with 62 Errors, 4 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run.

Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 6839.934 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
6 Infos, 4 Warnings, 0 Critical Warnings and 63 Errors encountered.
opt_design failed
opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 6839.934 ; gain = 0.000
ERROR: [Common 17-39] 'opt_design' failed due to earlier errors.

    while executing
"opt_design       -directive Explore"
    (file "implement.tcl" line 215)

I had previously had this error because of generate loops, since the same signal was being controlled by multiple inputs, but this time I can not solve this problem.
Could someone please help me with this error? Thanks in advance.
I leave attached the source code of the module in which I am having the problem, I also attach the file of the tcl script that I am using.

Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity g1_wbus_client_fifos_vhdl is
    generic(
            Almost_Full_Depth : std_logic_vector(9 downto 0) := "0111110100"
    );
    Port ( 
             i_aur_clk      : IN std_logic; 
             i_rst          : IN std_logic;    
             o_wbus_ready   : OUT std_logic;    
             i_wbus_wen     : IN std_logic;    
             i_wbus_addr    : IN std_logic_vector(31 DOWNTO 0);    
             i_wbus_data    : IN std_logic_vector(31 DOWNTO 0);    
             i_wbus_enable  : IN std_logic_vector(25 DOWNTO 0);    
             i_wbus_fws     : IN std_logic_vector(129 DOWNTO 0);    
             i_wbus_clk     : IN std_logic_vector(25 DOWNTO 0);    
             o_wbus_empty   : OUT std_logic_vector(25 DOWNTO 0);    
             i_wbus_ren     : IN std_logic_vector(25 DOWNTO 0);    
             o_wbus_count   : OUT std_logic_vector(259 DOWNTO 0);    
             o_wbus_valid   : OUT std_logic_vector(25 DOWNTO 0);    
             o_wbus_wdata   : OUT std_logic_vector(831 DOWNTO 0);    
             o_wbus_waddr   : OUT std_logic_vector(831 DOWNTO 0);    
             o_ro_wbus_debug : OUT std_logic_vector(31 DOWNTO 0);    
             o_test_points  : OUT std_logic_vector(3 DOWNTO 0)
             
    );
end g1_wbus_client_fifos_vhdl;

architecture Behavioral of g1_wbus_client_fifos_vhdl is

Component g1_ipcat_wbus_client_fifo
port(
          rst           : in std_logic;               -- input rst
          wr_clk        : in std_logic;           -- input wr_clk
          din           : in std_logic_vector(51 downto 0);               -- input [51 : 0] din
          wr_en         : in std_logic;                 -- input wr_en
          full          : out std_logic;                    -- output full
          wr_data_count : out std_logic_vector(9 downto 0);      -- output [9 : 0] wr_data_count
       
          -- The Client Port is connected to all the read signals
                                          
          rd_clk        : in std_logic;     -- input rd_clk
          rd_en         : in std_logic;     -- input rd_en
          dout          : out std_logic_vector(51 downto 0);             -- output [51 : 0] dout
          empty         : out std_logic;   -- output empty
          rd_data_count : out std_logic_vector(9 downto 0);     -- output [9 : 0] rd_data_count
          valid         : out std_logic    -- output valid    
);
end component;    
    type  wbus_count_type is array(0 to 25) of std_logic_vector(9 downto 0);
    SIGNAL almost_full      : std_logic_vector(25 DOWNTO 0);
    SIGNAL ffdin            : std_logic_vector(51 DOWNTO 0);
    SIGNAL ff_dout          : std_logic_vector(51 DOWNTO 0);
    SIGNAL ff_write_count   : std_logic_vector(9 DOWNTO 0); 
    SIGNAL wbus_count       : wbus_count_type;  
    SIGNAL wbr_d            : std_logic;
    SIGNAL upper_adrs_match : std_logic;
    SIGNAL wen              : std_logic_vector(25 downto 0);
    SIGNAL almost_full_d    : std_logic_vector(25 downto 0);
    SIGNAL wbus_addr_fws    : std_logic_vector(25 downto 0);
    SIGNAL ff_write_almost  : std_logic_vector(25 downto 0);
begin
    
    ffdin <= i_wbus_addr(19 downto 0) & i_wbus_data(31 downto 0);
    
    u_client : for idx in 0 to 25 generate
    
    begin       
        o_wbus_count(10*idx+9 downto 10*idx)    <= wbus_count(idx);
        
        upper_adrs_match                        <= '1'; 
        
        --Write only one fifo by decoding 5 address bits.
        wbus_addr_fws(idx)  <= '1' when (i_wbus_addr(20 downto 16) = i_wbus_fws(5*idx+4 downto 5*idx)) else '0';          
        wen(idx)            <= i_wbus_enable(idx) and i_wbus_wen and upper_adrs_match and wbus_addr_fws(idx);
        ff_write_almost(idx)     <= '1' when (ff_write_count > Almost_Full_Depth) else '0';
        almost_full_d(idx)  <= i_wbus_enable(idx) and ff_write_almost(idx);
        
         dc_amf: entity work.dreg_clr generic map(1)
         port map( 
                c   => i_aur_clk, 
                ar  => i_rst, 
                e   =>  '1', 
                d(0)   => almost_full_d(idx), 
                q(0)   => almost_full(idx)  
            );
        -- 52 bits x 512, First Word Fall Through.
        U_client_ff: g1_ipcat_wbus_client_fifo  
        port map(
          rst           => i_rst,               -- input rst
          wr_clk        => i_aur_clk,           -- input wr_clk
          din           => ffdin,               -- input [51 : 0] din
          wr_en         => wen(idx),                 -- input wr_en
          full          => open,                    -- output full
          wr_data_count => ff_write_count,      -- output [9 : 0] wr_data_count
       
          -- The Client Port is connected to all the read signals
                                          
          rd_clk        => i_wbus_clk(idx),     -- input rd_clk
          rd_en         => i_wbus_ren(idx),     -- input rd_en
          dout          => ff_dout,             -- output [51 : 0] dout
          empty         => o_wbus_empty(idx),   -- output empty
          rd_data_count => wbus_count(idx),     -- output [9 : 0] rd_data_count
          valid         => o_wbus_valid(idx)    -- output valid
        );            
        o_wbus_waddr(32*idx+31 downto 32*idx)   <= "0000000000000" & ff_dout(50 downto 32);
        o_wbus_wdata(32*idx+31 downto 32*idx)   <= ff_dout(31 downto 0);
            
    end generate u_client;
    wbr_d <= NOT (OR almost_full);
    
     dc_wbr : entity work.dreg_clr generic map(1)
       PORT MAP (
           c    => i_aur_clk,
           ar   => i_rst,
           e    => '1',
           d(0) => wbr_d,
           q(0) => o_wbus_ready);
           
    o_ro_wbus_debug <= X"E" & "00" & almost_full(25 DOWNTO 0);
    o_test_points <= x"0";              
end Behavioral;
 

Attachments

  • implement.tcl.rar
    2.8 KB · Views: 120

you are generating 26 copies of the g1_ipacat_wbus_client_fifo, but have all the wr_data_count and dout outputs shorted together. You can't have outputs of the generated instances connected to the same signal.
 

Could you please tell me in what line of my code does this short circuit happen?
 

I already solved it ... what I had to do is create a 26x52 matrix for ff_dout and another one of 26x10 for ff_write_count, leaving my code in the following way.

Code:
----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.02.2019 15:57:36
-- Design Name: 
-- Module Name: g1_wbus_client_fifos_vhdl - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;


entity g1_wbus_client_fifos_vhdl is
    generic(
            Almost_Full_Depth : std_logic_vector(9 downto 0) := "0111110100"
    );
    Port ( 
             i_aur_clk      : IN std_logic; 
             i_rst          : IN std_logic;    
             o_wbus_ready   : OUT std_logic;    
             i_wbus_wen     : IN std_logic;    
             i_wbus_addr    : IN std_logic_vector(31 DOWNTO 0);    
             i_wbus_data    : IN std_logic_vector(31 DOWNTO 0);    
             i_wbus_enable  : IN std_logic_vector(25 DOWNTO 0);    
             i_wbus_fws     : IN std_logic_vector(129 DOWNTO 0);    
             i_wbus_clk     : IN std_logic_vector(25 DOWNTO 0);    
             o_wbus_empty   : OUT std_logic_vector(25 DOWNTO 0);    
             i_wbus_ren     : IN std_logic_vector(25 DOWNTO 0);    
             o_wbus_count   : OUT std_logic_vector(259 DOWNTO 0);    
             o_wbus_valid   : OUT std_logic_vector(25 DOWNTO 0);    
             o_wbus_wdata   : OUT std_logic_vector(831 DOWNTO 0);    
             o_wbus_waddr   : OUT std_logic_vector(831 DOWNTO 0);    
             o_ro_wbus_debug : OUT std_logic_vector(31 DOWNTO 0);    
             o_test_points  : OUT std_logic_vector(3 DOWNTO 0)
             
    );
end g1_wbus_client_fifos_vhdl;

architecture Behavioral of g1_wbus_client_fifos_vhdl is

Component g1_ipcat_wbus_client_fifo
port(
          rst           : in std_logic;               -- input rst
          wr_clk        : in std_logic;           -- input wr_clk
          din           : in std_logic_vector(51 downto 0);               -- input [51 : 0] din
          wr_en         : in std_logic;                 -- input wr_en
          full          : out std_logic;                    -- output full
          wr_data_count : out std_logic_vector(9 downto 0);      -- output [9 : 0] wr_data_count
       
          -- The Client Port is connected to all the read signals
                                          
          rd_clk        : in std_logic;     -- input rd_clk
          rd_en         : in std_logic;     -- input rd_en
          dout          : out std_logic_vector(51 downto 0);             -- output [51 : 0] dout
          empty         : out std_logic;   -- output empty
          rd_data_count : out std_logic_vector(9 downto 0);     -- output [9 : 0] rd_data_count
          valid         : out std_logic    -- output valid    
);
end component;    
    type  wbus_count_type is array(0 to 25) of std_logic_vector(9 downto 0);
    type  array_26x10 is array(0 to 25) of std_logic_vector(9 downto 0);
    type  array_26x52 is array(0 to 25) of std_logic_vector(51 downto 0);
    SIGNAL almost_full      : std_logic_vector(25 DOWNTO 0);
    SIGNAL ffdin            : std_logic_vector(51 DOWNTO 0);
    SIGNAL ff_dout          : array_26x52;
    SIGNAL ff_write_count   : array_26x10;  
    SIGNAL wbus_count       : wbus_count_type;  
    SIGNAL wbr_d            : std_logic;
    SIGNAL upper_adrs_match : std_logic;
    SIGNAL wen              : std_logic_vector(25 downto 0);
    SIGNAL almost_full_d    : std_logic_vector(25 downto 0);
    SIGNAL wbus_addr_fws    : std_logic_vector(25 downto 0);
begin
    
    ffdin <= i_wbus_addr(19 downto 0) & i_wbus_data(31 downto 0);
    
    u_client : for idx in 0 to 25 generate
    
    begin       
        o_wbus_count(10*idx+9 downto 10*idx)    <= wbus_count(idx);
        
        upper_adrs_match                        <= '1'; 
        
        --Write only one fifo by decoding 5 address bits.
        wbus_addr_fws(idx)  <= '1' when (i_wbus_addr(20 downto 16) = i_wbus_fws(5*idx+4 downto 5*idx)) else '0';          
        wen(idx)            <= i_wbus_enable(idx) and i_wbus_wen and upper_adrs_match and wbus_addr_fws(idx);
--        ff_write_almost(idx)     <= '1' when (ff_write_count > Almost_Full_Depth) else '0';
        almost_full_d(idx)  <= i_wbus_enable(idx) and '1' when (ff_write_count(idx) > Almost_Full_Depth) else '0';
        
         dc_amf: entity work.dreg_clr generic map(1)
         port map( 
                c   => i_aur_clk, 
                ar  => i_rst, 
                e   =>  '1', 
                d(0)   => almost_full_d(idx), 
                q(0)   => almost_full(idx)  
            );
        -- 52 bits x 512, First Word Fall Through.
        U_client_ff: g1_ipcat_wbus_client_fifo  
        port map(
          rst           => i_rst,               -- input rst
          wr_clk        => i_aur_clk,           -- input wr_clk
          din           => ffdin,               -- input [51 : 0] din
          wr_en         => wen(idx),                 -- input wr_en
          full          => open,                    -- output full
          wr_data_count => ff_write_count(idx),      -- output [9 : 0] wr_data_count
       
          -- The Client Port is connected to all the read signals
                                          
          rd_clk        => i_wbus_clk(idx),     -- input rd_clk
          rd_en         => i_wbus_ren(idx),     -- input rd_en
          dout          => ff_dout(idx),             -- output [51 : 0] dout
          empty         => o_wbus_empty(idx),   -- output empty
          rd_data_count => wbus_count(idx),     -- output [9 : 0] rd_data_count
          valid         => o_wbus_valid(idx)    -- output valid
        );            
        o_wbus_waddr(32*idx+31 downto 32*idx)   <= "0000000000000" & ff_dout(idx)(50 downto 32);
        o_wbus_wdata(32*idx+31 downto 32*idx)   <= ff_dout(idx)(31 downto 0);
            
    end generate u_client;
    wbr_d <= NOT (OR almost_full);
    
     dc_wbr : entity work.dreg_clr generic map(1)
       PORT MAP (
           c    => i_aur_clk,
           ar   => i_rst,
           e    => '1',
           d(0) => wbr_d,
           q(0) => o_wbus_ready);
           
    o_ro_wbus_debug <= X"E" & "00" & almost_full(25 DOWNTO 0);
    o_test_points <= x"0";              
end Behavioral;

Thanks for the help.
 

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