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    Help me with the analys of this sequential circuit

    Im studying for an exam and im stuck on this one for three days

    The task is to analyze the circuit with truth table and at last a state diagram.

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  2. #2
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    Re: Help me with the analys of this sequential circuit

    Hi,

    Can't check pdfs now but from memory, it looks like it might be a ripple counter. Synchronous or asynchronous..., can't say without checking either.



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    Re: Help me with the analys of this sequential circuit

    Hi,

    Where is the difficulty?

    Use a pencil and a sheet of paper.
    The start with the first gate: Clk = 0 and D = 0. Unknown output state.
    --> What happens after the first rising clock edge with the outputs? --> now you get known output stages.
    These ouputs become the inputs of the next gate.
    --> What happens with the ouputs of the second gate after the second rising clock edge? They becom known.
    These ouputs become the inputs of the next gate.
    --> What happens with the ouputs of the third gate after the third rising clock edge? They becom known.
    These outputs become the input of the first stage.

    With 3 FF you get maximum 8 different states.
    To create a complete loop of known states you need to assume that there are 7 clock periods (worst case) with unknown states.
    (in your case it is less)
    And then you need maximum additional 8 clock periods to get a full loop of all known states (in your case it is less)

    Show us your drawing...

    Klaus
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    Re: Help me with the analys of this sequential circuit

    Here is my truth table thus far, i have not bothered with clock(X) is 0 because it is always the same state as the input according to what i can see this far.

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    Re: Help me with the analys of this sequential circuit

    Hi,

    I think a timing diagram is more helpful...

    Klaus
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    Re: Help me with the analys of this sequential circuit

    It is synchronous because all three flip flops use the same clock and the same edge of the clock.

    I do not think your truth table Q's are consistent.
    First row has QA, QB snd Qc = 0, yielding the D, S, R, J and K you have listed. But the three Q's after the clock will not be 0, 0, 0.
    Second row Q's should match the first row Q after the clock, and they do not.

    If they did match, then your truth table says the three Qs are always zero.

    I think you want to continue your truth table a few more lines.
    If you do it in a spreadsheet, you can copy it down as many rows as you like.
    The equations are straight forward. D = Qc prior row, S = Qa prior row, toggle = 1- prior row for JK ff if J = 1, etc

    I got a repeating pattern regardless of Q at start. It just takes a different number of steps for it to settle down.

    If this is studying for the test, its ok to ask the forum.
    If this is an actual test, then it is inappropriate to ask the forum, you need to ask your instructor.



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    Re: Help me with the analys of this sequential circuit

    Thank you all for your replys, and dont worry this is an old exam from 2013 im practicing on.

    But im still not there yet, i tried to do a timing diagram and im stuck in a loop. All three flip flops are activated on falling edges. But from what i can see Qa have 0 at first tick, that means that S gets 0 and R=1 which means Qb have 0 as output, JK then gets 0 and 1 which sends a 0 to Qc and a 0 to D input and the loop starts again?

    Am i on the right track or am i missing something?



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    Re: Help me with the analys of this sequential circuit

    First row has QA, QB snd Qc = 0, yielding the D, S, R, J and K you have listed. But the three Q's after the clock will not be 0, 0, 0.
    It actually is, the table is correct.

    You get either constant 000 or a partly repeating pattern, the repeated states are 100, 010, 001, 100, as indicated by the next state table. A complete state diagram should supplement the next state table.


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    Re: Help me with the analys of this sequential circuit

    I tried to build the circuit in logisim and as far as i can see the truth table is correct, the state diagram should then look like this:

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    Where the arrows are only when we get clock is 1, because when clock is 0 "it is always the same state as the input".



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    Re: Help me with the analys of this sequential circuit

    Yes, correct state diagram.

    Where the arrows are only when we get clock is 1
    According to schematic symbol, the flip flops are negative edge triggered, state is advancing on 1->0 transition of the clock input.



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  11. #11
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    Re: Help me with the analys of this sequential circuit

    Agreed
    I had an error in my spreadsheet



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