Why my 2-digit counter w/VHDL didn't work?

entity twodigitcounter is
  Port ( 
  
  clk : in std_logic;
  digit1,digit2 : out integer range 0 to 9
  );
end twodigitcounter;

architecture Behavioral of twodigitcounter is

shared variable temp1,temp2 : integer range 0 to 9;
begin
proc1:process(clk)

begin

    if rising_edge(clk) then
        if temp1 = 9 then
            temp1:=0;
        else
            temp1:=temp1+1;
        end if;
    end if;
end process proc1;

proc2:process(clk)

begin

    if rising_edge(clk) then
        if temp1=9 then
            if temp2=9 then
                temp2:=0;
            else   
            temp2:=temp2+1;
            end if;
        end if; 
   end if;
end process proc2;

digit1 <= temp1;
digit2 <= temp2;

end Behavioral;

entity twodigitcounter_tb is
--  Port ( );
end twodigitcounter_tb;

architecture Behavioral of twodigitcounter_tb is

signal clk :  std_logic;
signal digit1,digit2 :  integer range 0 to 9;

component twodigitcounter 
port(
  clk : in std_logic;
  digit1,digit2 : out integer range 0 to 9
  );
end component;


begin

uut:twodigitcounter port map(

clk => clk,
digit1 => digit1,
digit2 => digit2

);

process 
begin
    if clk /= '1' then clk <= '1';
    else clk <= '0';
    end if;
    wait for 10 ns;
    end process;
    

end Behavioral;