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    Clock domain crossing problem

    This is an interview question I found:
    I have three clock domains A, B and C.
    I have some data coming from clock domain A and clock domain B.
    I want to do some combinational operation and send the resulting data to clock domain C.
    How can I do this?

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    Re: Clock domain crossing problem

    Why not simple synchronizers?
    Really, I am not Sam.



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    Re: Clock domain crossing problem

    Quote Originally Posted by ThisIsNotSam View Post
    Why not simple synchronizers?
    You mean to say that synchronize data from clock domain A and B to clock domain C and then do the combinational operation?



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    Re: Clock domain crossing problem

    Hi,

    This is how I´d do it.

    In detail it depends on signal timings and clock frequencies.

    Example:
    It will fail if signal A is a 100ns pulse and Clock_C frequency is 1MHz (1000ns).
    It will work when signal A is a 1000ns pulse while Clock_C frequency is 10MHz (100ns).

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: Clock domain crossing problem

    Quote Originally Posted by biju4u90 View Post
    This is an interview question I found:
    I have three clock domains A, B and C.
    I have some data coming from clock domain A and clock domain B.
    I want to do some combinational operation and send the resulting data to clock domain C.
    How can I do this?
    1. You cannot simply synchronize data from clock domain A and B to clock domain C and then perform the combinational operation. This will result in classic problem of re-convergence. With synchronizers you cannot guarantee that data will be sampled in 2 clock cycles (assuming double flops for synchronizers). There can be delay. Hence, when output of 2 synchronizers re-converge at a combinational logic, you cannot guarantee that it is functionally correct.
    2. Because of #1, you will have to sample data from clock domain A to clock domain B (i.e add synchronizer from A->B), then perform combinational logic operation. Now one more problems arise. You cannot simply synchronize data of combinational logic to clock domain C. Combinational logic in front of synchronizer might result in glitch to be sampled (again functional problem)
    3. Because of #2, you will have to add a flop to output of combinational logic (clock of course from B). Now you are good to add synchronizer to move to clock domain C.

    Let me know if you have any more questions.


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    Re: Clock domain crossing problem

    Quote Originally Posted by swabhi812 View Post
    1. You cannot simply synchronize data from clock domain A and B to clock domain C and then perform the combinational operation. This will result in classic problem of re-convergence. With synchronizers you cannot guarantee that data will be sampled in 2 clock cycles (assuming double flops for synchronizers). There can be delay. Hence, when output of 2 synchronizers re-converge at a combinational logic, you cannot guarantee that it is functionally correct.
    2. Because of #1, you will have to sample data from clock domain A to clock domain B (i.e add synchronizer from A->B), then perform combinational logic operation. Now one more problems arise. You cannot simply synchronize data of combinational logic to clock domain C. Combinational logic in front of synchronizer might result in glitch to be sampled (again functional problem)
    3. Because of #2, you will have to add a flop to output of combinational logic (clock of course from B). Now you are good to add synchronizer to move to clock domain C.

    Let me know if you have any more questions.
    while all of this is true, OP's question is so vague that I don't know if it applies. I mean, why would you have any output to be combinational to begin with? This is frowned up.
    Really, I am not Sam.



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    Re: Clock domain crossing problem

    Quote Originally Posted by ThisIsNotSam View Post
    while all of this is true, OP's question is so vague that I don't know if it applies. I mean, why would you have any output to be combinational to begin with? This is frowned up.
    This is interview question which test possible issues with synchronizations. Nothing more than that :)



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    Re: Clock domain crossing problem

    Quote Originally Posted by swabhi812 View Post
    1. You cannot simply synchronize data from clock domain A and B to clock domain C and then perform the combinational operation. This will result in classic problem of re-convergence. With synchronizers you cannot guarantee that data will be sampled in 2 clock cycles (assuming double flops for synchronizers). There can be delay. Hence, when output of 2 synchronizers re-converge at a combinational logic, you cannot guarantee that it is functionally correct.
    2. Because of #1, you will have to sample data from clock domain A to clock domain B (i.e add synchronizer from A->B), then perform combinational logic operation. Now one more problems arise. You cannot simply synchronize data of combinational logic to clock domain C. Combinational logic in front of synchronizer might result in glitch to be sampled (again functional problem)
    3. Because of #2, you will have to add a flop to output of combinational logic (clock of course from B). Now you are good to add synchronizer to move to clock domain C.

    Let me know if you have any more questions.
    Looks like a perfect answer to the question. Thank you for the help.



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    Re: Clock domain crossing problem

    Quote Originally Posted by swabhi812 View Post
    1. You cannot simply synchronize data from clock domain A and B to clock domain C and then perform the combinational operation. This will result in classic problem of re-convergence. With synchronizers you cannot guarantee that data will be sampled in 2 clock cycles (assuming double flops for synchronizers). There can be delay. Hence, when output of 2 synchronizers re-converge at a combinational logic, you cannot guarantee that it is functionally correct.
    2. Because of #1, you will have to sample data from clock domain A to clock domain B (i.e add synchronizer from A->B), then perform combinational logic operation. Now one more problems arise. You cannot simply synchronize data of combinational logic to clock domain C. Combinational logic in front of synchronizer might result in glitch to be sampled (again functional problem)
    3. Because of #2, you will have to add a flop to output of combinational logic (clock of course from B). Now you are good to add synchronizer to move to clock domain C.

    Let me know if you have any more questions.
    in #3, you cant just add synchronizers if you the data is multibit.



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    Re: Clock domain crossing problem

    Quote Originally Posted by stanford View Post
    in #3, you cant just add synchronizers if you the data is multibit.
    Of course you cannot add synchronizer for multi bit data and this is due to reason #1 (no guarantee for delay). You will need DMUX synchronizer or FIFO for multi bit data.



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