+ Post New Thread
Results 1 to 19 of 19
  1. #1
    Newbie level 5
    Points: 57, Level: 1

    Join Date
    Mar 2019
    Posts
    9
    Helped
    0 / 0
    Points
    57
    Level
    1

    FPGA synthesizes and simulates correctly but doesnt work on hardware

    Hi, I'm trying to write a simple program for sending data from the fpga to a computer through a usb to rs232 converter, Ftdi Ft232rl. I want to send 2 bytes of data then '\r\n'. I am using a lattice MachXO3L-6900C FPGA and simulating with Active-HDL lattice edition. Also I am new to FPGAs so I dont really know what I am doing as I am teaching myself how to use it. Could someone help me find out what is going on and how to fix it. This is the overall view of the program

    Click image for larger version. 

Name:	fpgahelp.png 
Views:	11 
Size:	13.9 KB 
ID:	151663
    CompClock is always outputting the clock signals, in this case its 133Mhz from osc_int port (it is the clock generated by the fpga's internal osc) and the P_UARTCLOCK is a 10Mhz clock.
    CompUart is supposed to output the serial data on P_UARTDAT, when it transfers 4 bytes UARTREADY pulses for one clock cycle and resets the module to send everything again. I'm having two problems that I have no Idea how to fix the uartclock and the uart compontent itself.

    The Uartclock is working in the fpga but using a logic analyzer I found the it was outputting an unstable clock signal which switches between 1.33Mhz and 2Mhz waveform below. this clock signal is generated from the internal 133MHz by lattice's PLL, so I don't know why it is so far off. when simulating this works correctly and I have a 10MHz clock. this the the overall view of the clock component
    Click image for larger version. 

Name:	fpgawave.png 
Views:	16 
Size:	18.2 KB 
ID:	151664Click image for larger version. 

Name:	FPGACLCOK.png 
Views:	5 
Size:	17.3 KB 
ID:	151665

    the Uart component is outputting nothing on the fpga, though it outputs on the simulation. So I have no Idea what might be wrong other than the clock here is the map for the uart component Click image for larger version. 

Name:	fpgauart.png 
Views:	6 
Size:	14.4 KB 
ID:	151666
    I am keeping every file on github here in case if someone wants to see.
    The the structure in the VHDL files is like this
    Main
    • CompClock
      • CompPLL (Lattice generated)



    • CompUART
      • CompRS232
      • CompDataSelect (where the 16 bits data is seperated into two and \r\n is sent one after the other)


    here is the vhdl main vhdl File and the clock vhdl file
    Code:
    library  ieee;
    use  ieee.std_logic_1164.all;
    
    entity Main is
    	 port ( 
    	 --T_test: out std_logic;
    	 P_UART_TX: out std_logic
    		   );
    end Main;
    
    architecture behav of Main is
    	signal S_MainClock : STD_LOGIC :='0';
    	signal S_UARTClock : STD_LOGIC :='0';
    	signal S_TX_DATA   : std_logic_vector(15 downto 0) := X"AB7C";
    	signal S_UART_READY: std_logic; 
    	signal S_UART_RESET: std_logic :='1';  
    	
    	COMPONENT Clock
    	-- synthesis translate_on
    		port (stdby : in std_logic;
    		      osc_int: out std_logic;
    			  p_UartClock : out std_logic;
    			  P_resetclock : out std_logic 
    		   );
    	END COMPONENT;
    	
    	COMPONENT UART
    		PORT(
    				P_UARTDATA: out std_logic ;
    				UARTREADY: out std_logic;
    				P_CLK: in std_logic; 
    				P_Data: in std_logic_vector(15 downto 0);
    				P_Reset: in std_logic;
    				P_STDBY: in std_logic
    			);
    			
    	END COMPONENT;
    	
    begin
    
    	CompClock: Clock
    	-- synthesis translate_on
    	PORT MAP(  
    				STDBY => '0',
    				osc_int => S_MainClock, 
    				p_UartClock => S_UARTClock,
    				P_resetclock => S_UART_RESET
    			);
    			
    	CompUART: UART
    	PORT MAP(
    				P_UARTDATA => P_UART_TX,
    				UARTREADY => S_UART_READY,
    				P_CLK => S_UARTClock,
    				P_Data => S_TX_DATA,
    				P_Reset => S_UART_READY,--S_UART_RESET,
    				P_STDBY => '0'	
    			);
    	--T_TEST <= S_UARTClock;	
    end behav;
    Code:
    library  ieee;
    use  ieee.std_logic_1164.all;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    
    -- For Main Clock --
    library machXO3l;
    use machXO3l.all;
    --------------------
    
    entity Clock is
    	 port (stdby : in std_logic;
    		   osc_int: out std_logic;
    		   p_UartClock : out std_logic;
    		   P_resetclock : out std_logic 
    		   );
    end Clock;
    
    architecture Clock_behav of Clock is
    	signal S_InternalClock : std_logic;
    	signal S_mainClock : std_logic; 
    	signal S_UARTClock : std_logic;  
    	signal S_PLLEN : std_logic;
    	signal CLK_DIV : std_logic_vector (13 downto 0) := (others => '0');
    	
    	COMPONENT OSCH
    	-- synthesis translate_off
    		GENERIC (NOM_FREQ: string := "133.00");
    	-- synthesis translate_on
    		PORT (STDBY : IN std_logic;
    			  OSC : OUT std_logic
    				);
    	END COMPONENT;
    	attribute NOM_FREQ : string;
    	attribute NOM_FREQ of Clock : label is "133.00";
    	
    	COMPONENT ClkPll
    	-- synthesis translate_on
    		PORT (CLKI : IN std_logic;
    			  ENCLKOP : IN std_logic;
    			  CLKOP : OUT std_logic;
    			  ENCLKOS : IN std_logic;
    			  CLKOS : OUT std_logic
    				);
    	END COMPONENT;
    	
    begin
    	
    	Clock: OSCH
    	-- synthesis translate_off
    	GENERIC MAP( NOM_FREQ =>"133.00" )
    	-- synthesis translate_on
    	PORT MAP (  STDBY => '0',
    				OSC => S_InternalClock
    	);
    	
    	CompPll: ClkPll
    	Port Map( CLKI => S_InternalClock,
    			  ENCLKOP => S_PLLEN,
    			  CLKOP => S_UARTClock,
    			  CLKOS => S_mainClock,
    			  ENCLKOS => '1'
    	);
    	
    	-- clock divider
        process (S_UARTClock)
        begin
            if (rising_edge(S_UARTClock)) then
                CLK_DIV <= CLK_DIV + '1';
            end if;
        end process;
    	
    	S_PLLEN <= not stdby;
    	osc_int <= S_mainClock;
    	p_UartClock <= S_UARTClock;
    	P_resetclock <= CLK_DIV(13);
    end Clock_behav;

  2. #2
    Advanced Member level 5
    Points: 22,696, Level: 36
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,345
    Helped
    959 / 959
    Points
    22,696
    Level
    36

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    You've got a lot of things wrong here and you're trying to fix everything at once. Bad idea.

    I would suggest you first resolve the clock problem. You're expecting 10MHz, but getting an asymmetric 1MHz clock. I wouldn't say it's 'switching between 1.33 and 2MHz'. What you've shown looks a very stable 1MHz clock with a 67% duty cycle.

    Once you get the clock working, start debugging the rest of the system.


    1 members found this post helpful.

  3. #3
    Super Moderator
    Points: 30,147, Level: 42
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    6,938
    Helped
    1655 / 1655
    Points
    30,147
    Level
    42

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by barry View Post
    What you've shown looks a very stable 1MHz clock with a 67% duty cycle.
    barry, you need to see an optometrist , there is definitely a pattern but it's not a 67% duty cycle. We have low going pulses of equal duration with alternating high pulses of 1x and 2x of the low pulse width.

    Quote Originally Posted by barry View Post
    Once you get the clock working, start debugging the rest of the system.
    Agree completely, that weird clock behaviour needs to be addressed first. Though I can't make heads or tails from the description of the design, nor understand anything since the design is buried behind a bunch of schematic based blocks that the tools want you to use to permanently lock you into that FPGA companies products.



  4. #4
    Advanced Member level 5
    Points: 22,696, Level: 36
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,345
    Helped
    959 / 959
    Points
    22,696
    Level
    36

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by ads-ee View Post
    barry, you need to see an optometrist , there is definitely a pattern but it's not a 67% duty cycle. We have low going pulses of equal duration with alternating high pulses of 1x and 2x of the low pulse width.
    Yeah, you're right. But it IS periodic.



    •   AltAdvertisment

        
       

  5. #5
    Newbie level 5
    Points: 57, Level: 1

    Join Date
    Mar 2019
    Posts
    9
    Helped
    0 / 0
    Points
    57
    Level
    1

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    ok, I`ll try to fix the clock first I just can`t imagine why it is acting this way in the hardware or why one part does nothing



  6. #6
    Newbie level 5
    Points: 57, Level: 1

    Join Date
    Mar 2019
    Posts
    9
    Helped
    0 / 0
    Points
    57
    Level
    1

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    update, I put a simple clock divider written in vhdl and the clock signal is mostly at 125kHz, with sometimes with a one 10us pulse. I'm going to look at the signal generated by the internal oscillator and see how it is behaving (the logic analyzer i have isn't fast enough for 113MHz)



    •   AltAdvertisment

        
       

  7. #7
    Super Moderator
    Points: 30,147, Level: 42
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    6,938
    Helped
    1655 / 1655
    Points
    30,147
    Level
    42

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Why are you using a logic analyzer, use a oscilloscope to look at the clock and if you expect there are issues with glitches, then use a scope with a persistence mode and see if there is anything wrong with the clock.

    Makes me wonder if you were having a sampling problem using a logic analyzer to look at the clock instead of a proper scope.



  8. #8
    Super Moderator
    Points: 252,800, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,041
    Helped
    13398 / 13398
    Points
    252,800
    Level
    100

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    I wonder where the parameters for the ClkPll primitive are set? Is it a wizard generated component?



    •   AltAdvertisment

        
       

  9. #9
    Newbie level 5
    Points: 57, Level: 1

    Join Date
    Mar 2019
    Posts
    9
    Helped
    0 / 0
    Points
    57
    Level
    1

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by FvM View Post
    I wonder where the parameters for the ClkPll primitive are set? Is it a wizard generated component?
    it is a wizard generated component.



  10. #10
    Advanced Member level 5
    Points: 22,696, Level: 36
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,345
    Helped
    959 / 959
    Points
    22,696
    Level
    36

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by kiyoshi7 View Post
    update, I put a simple clock divider written in vhdl and the clock signal is mostly at 125kHz, with sometimes with a one 10us pulse. I'm going to look at the signal generated by the internal oscillator and see how it is behaving (the logic analyzer i have isn't fast enough for 113MHz)
    We don’t know what your “simple clock didvider” is, but ASSUMING that’s not the problem, then maybe your 133 MHz clock is the problem. Is it properly terminated? Are the voltage levels correct? Are your timing constraints correct?



  11. #11
    Newbie level 5
    Points: 57, Level: 1

    Join Date
    Mar 2019
    Posts
    9
    Helped
    0 / 0
    Points
    57
    Level
    1

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by ads-ee View Post
    Why are you using a logic analyzer, use a oscilloscope to look at the clock and if you expect there are issues with glitches, then use a scope with a persistence mode and see if there is anything wrong with the clock.

    Makes me wonder if you were having a sampling problem using a logic analyzer to look at the clock instead of a proper scope.
    sorry for taking so long. you were right, I had forgotten that my logic analyzer isn't fast enough for this task. I checked the 10 MHz UART clock with an Oscilloscope and the clock seems to be stable at 10 Mhz, the value it is supposed to be.

    The Uart portion however is not outputting anything. So the problem must be either in UART.vhd, DataSelect.vhd or UART_TX.vhd.
    UART.vhd is supposed to connect the other two scripts and not much else, I created this block just to be easier to use in main.vhd
    UART_TX.vdh has the actual uart component that gets parallel data and sends the data, 8 bits at a time this code was taken from nandland.com.
    DataSelect.vhd controlls UART_TX. since my data is 16 bits it separates the data into two bits and new line( in uart_tx sends 32bits)
    Do you have any recommendations in how to proceed debugging the hardware, I'd imagin in dataSelect, but I honsetly can't figure out where?



  12. #12
    Newbie level 5
    Points: 57, Level: 1

    Join Date
    Mar 2019
    Posts
    9
    Helped
    0 / 0
    Points
    57
    Level
    1

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by barry View Post
    Is it properly terminated?
    From the netlist Analyzer that diamond generates, I believe that it is (all but the port P_STDBY of UART.vhd, it is declared but it isn't being used in the code)

    Quote Originally Posted by barry View Post
    Are the voltage levels correct? Are your timing constraints corr
    I don't know how to check that. The only resource the I actually used to learn how to use a fpga is the book Free Range VHDL, so there is a lot I don't understand and am still trying to figure out.



  13. #13
    Advanced Member level 5
    Points: 22,696, Level: 36
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,345
    Helped
    959 / 959
    Points
    22,696
    Level
    36

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by kiyoshi7 View Post
    From the netlist Analyzer that diamond generates, I believe that it is (all but the port P_STDBY of UART.vhd, it is declared but it isn't being used in the code)


    I don't know how to check that. The only resource the I actually used to learn how to use a fpga is the book Free Range VHDL, so there is a lot I don't understand and am still trying to figure out.
    I think you are confusing pin-mapping with termination. Just because the signal shows up in the netlist doesn't mean it's terminated properly on the PCB. Are you using a custom board, or an off-the-shelf one?

    If you use an oscilloscope, you will be able to see what your voltage levels are. And your constraint file will define what voltage levels (e.g. LVCMOS, LVTTL, etc.) the the FPGA is expecting. Timing constraints are also defined in a constraint file: something as simple as declaring the maximum clock frequency.



  14. #14
    Newbie level 5
    Points: 57, Level: 1

    Join Date
    Mar 2019
    Posts
    9
    Helped
    0 / 0
    Points
    57
    Level
    1

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by barry View Post
    I think you are confusing pin-mapping with termination. Just because the signal shows up in the netlist doesn't mean it's terminated properly on the PCB. Are you using a custom board, or an off-the-shelf one?
    it an off the shelf fpga


    Quote Originally Posted by barry View Post
    If you use an oscilloscope, you will be able to see what your voltage levels are. And your constraint file will define what voltage levels (e.g. LVCMOS, LVTTL, etc.) the the FPGA is expecting. Timing constraints are also defined in a constraint file: something as simple as declaring the maximum clock frequency.
    I'll try to find this constraint file, but I have no idea where diamond keeps it, i looked at some of the timing analysis view tool but I dont think thats it. out of curiosity is it the spreadsheet view?



  15. #15
    Advanced Member level 5
    Points: 22,696, Level: 36
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,345
    Helped
    959 / 959
    Points
    22,696
    Level
    36

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    I haven’t used Diamond in quite a few years, but I believe the constraints file is *.lpf. I don’t recall if that’s just placement or timing as well



  16. #16
    Newbie level 5
    Points: 57, Level: 1

    Join Date
    Mar 2019
    Posts
    9
    Helped
    0 / 0
    Points
    57
    Level
    1

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    I`m looking at the reports generated by diamond and I found this in latice LSE: top,
    Code:
    WARNING - synthesis: c:/users/daniel/desktop/projects/fpga/lattice/rs232/main.vhd(14): using initial value "1010101101111100" for s_tx_data since it is never assigned. VHDL-1303
    WARNING - synthesis: c:/users/daniel/desktop/projects/fpga/lattice/rs232/main.vhd(9): replacing existing netlist Main(behav). VHDL-1205
    Top module name (VHDL): Main
    Loading NGL library 'C:/lscc/diamond/3.10_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
    Loading NGL library 'C:/lscc/diamond/3.10_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
    Loading NGL library 'C:/lscc/diamond/3.10_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
    Loading NGL library 'C:/lscc/diamond/3.10_x64/ispfpga/or5g00/data/orc5glib.ngl'...
    Loading device for application map from file 'xo3c6900.nph' in environment: C:/lscc/diamond/3.10_x64/ispfpga.
    Package Status:                     Final          Version 1.16.
    Top-level module name = Main.
    WARNING - synthesis: Initial value found on net T_test will be ignored due to unrecognized driver type
    WARNING - synthesis: Initial value found on net r_TX_DV will be ignored due to unrecognized driver type
    WARNING - synthesis: Initial value found on net o_SendData will be ignored due to unrecognized driver type
    
    
    
    GSR instance connected to net \CompUART/CompDataSelect/i_reset_N_73.
    WARNING - synthesis: Initial value found on instance \CompUART/CompDataSelect/s_counter_i0 will be ignored.
    WARNING - synthesis: Initial value found on instance \CompUART/CompDataSelect/s_counter_i1 will be ignored.
    WARNING - synthesis: Initial value found on instance \CompUART/CompDataSelect/s_counter_i2_reset will be ignored.
    WARNING - synthesis: Initial value found on instance \CompUART/CompDataSelect/s_counter_2__N_70_I_0_reset will be ignored.
    WARNING - synthesis: mRegister \CompUART/CompDataSelect/s_counter_2__N_70_I_0_reset is stuck at Zero
    Duplicate register/latch removal. \CompUART/CompRS232/r_TX_Data_i4 is a one-to-one match with \CompUART/CompRS232/r_TX_Data_i6.
    Applying 200.000000 MHz constraint to all clocks
    
    WARNING - synthesis: No user .sdc file.
    Results of NGD DRC are available in Main_drc.log.
    Loading NGL library 'C:/lscc/diamond/3.10_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
    Loading NGL library 'C:/lscc/diamond/3.10_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
    Loading NGL library 'C:/lscc/diamond/3.10_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
    Loading NGL library 'C:/lscc/diamond/3.10_x64/ispfpga/or5g00/data/orc5glib.ngl'...
    All blocks are expanded and NGD expansion is successful.
    Writing NGD file UART_impl1.ngd.
    looking I LPF files in the project directory directory I found two( there were many but they were for devices it seems) here is what is in them
    Code:
    #BLOCK ASYNCPATHS;
    #BLOCK RESETPATHS;
    
    #FREQUENCY 200.000000 MHz;
    Code:
    BLOCK RESETPATHS ;
    BLOCK ASYNCPATHS ;
    LOCATE COMP "P_UART_TX" SITE "B5" ;
    LOCATE COMP "T_test" SITE "B4" ;
    I don't think this is what you are asking for so I am still looking around. Looking at the lattice diamond users guide I got the impression that most of the information is separated into chucks that are viewable withing the diamond.
    the only place I am finding voltage levels is in the power calculator that give me this report:
    Code:
    Power Calculator - Report
    Lattice Diamond  Version 3.10.3.144 - Power Calculator
    Copyright (C) 1992-2018 Lattice Semiconductor Corporation.
    All Rights Reserved.
    
    Power Model Information
    Format Revision : 1.11, 1.03, 1.00, 1.02 - Software
    Values Revision : 1.16, 1.08, 1.00, 1.05 - Software
    Power Model Status : Final    Version 1.16
    
    Design and Device Details
    Power Project Name : Untitled - User/Default/NCD Provided
    Design Name : Main - User/Default/NCD Provided
    Family : MachXO3L - User/Default/NCD Provided
    Device : LCMXO3L-6900C - User/Default/NCD Provided
    Package : CABGA256 - User/Default/NCD Provided
    Operating : Commercial - User/Default/NCD Provided
    Part Number : LCMXO3L-6900C-5BG256C - User/Default/NCD Provided
    Process Type : Typical - User/Default/NCD Provided
    
    Power Supplies
    Vccio 3.3 : 3.300 V - User/Default/NCD Provided
    Vccio 2.5 : 2.500 V - User/Default/NCD Provided
    Vccio 1.8 : 1.800 V - User/Default/NCD Provided
    Vccio 1.5 : 1.500 V - User/Default/NCD Provided
    Vccio 1.2 : 1.200 V - User/Default/NCD Provided
    Vcc : 3.300 V - User/Default/NCD Provided
    
    Power Summary
    Power Est. Design Vccio 3.3 : 0.000000 W
    Power Est. Design Vccio 2.5 : 0.000011 W
    Power Est. Design Vccio 1.8 : 0.000000 W
    Power Est. Design Vccio 1.5 : 0.000000 W
    Power Est. Design Vccio 1.2 : 0.000000 W
    Power Est. Design Vcc : 0.101461 W
    Total Power Est. Design  : 0.101472 W
    
    Icc Summary
    Icc Est. Design Vccio 3.3 : 0.000000 A
    Icc Est. Design Vccio 2.5 : 0.000004 A
    Icc Est. Design Vccio 1.8 : 0.000000 A
    Icc Est. Design Vccio 1.5 : 0.000000 A
    Icc Est. Design Vccio 1.2 : 0.000000 A
    Icc Est. Design Vcc : 0.030746 A
    Total Icc Est. Design  : 0.030750 A
    
    IO Bank Summary
    IO Bank Used : 2
    
    Peak Startup
    VCC : 0.0790 A 
    VCCIO : 0.0170 A 
    
    Thermal Summary
    Board Selection : Medium Board
    Heat Sink : No Heat Sink
    Air Flow : 200 LFM
    Ambient Temperature : 25 C
    Effective Theta-JA : 18.85
    Junction Temperature : 26.91 C
    Maximum Safe Ambient : 81.77 C
    
    Utilization Details
    
    Logic
    LUTs Used : 43
    Dist. RAM Slices Used : 0
    Ripple Slices Used : 4
    Registers Used : 36
    Dynamic Power (W) : 0.000000
    Static Power (W) : 0.014010
    Total Power (W) : 0.014010
    
    Clocks
    PCLKs Used : 9
    SCLKs Used : 7
    ECLKs Used : 0
    Dynamic Power (W) : 0.000000
    Static Power (W) : 0.000528
    Total Power (W) : 0.000528
    
    I/O
    I/O Used : 6
    Dynamic Power (W) : 0.000000
    Static Power (W) : 0.000404
    Total Power (W) : 0.000404
    
    Block RAM
    EBR Blocks Used : 0
    Dynamic Power (W) : 0.000000
    Static Power (W) : 0.000524
    Total Power (W) : 0.000524
    
    PLL
    PLL Used : 1
    Dynamic Power (W) : 0.000000
    Static Power (W) : 0.021228
    Total Power (W) : 0.021228
    
    DQSDLL
    DQSDLL Used : 0
    Dynamic Power (W) : 0.000000
    Static Power (W) : 0.000017
    Total Power (W) : 0.000017
    
    DLLDEL
    DLLDEL Used : 0
    Dynamic Power (W) : 0.000000
    Static Power (W) : 0.000015
    Total Power (W) : 0.000015
    
    EFB
    I2C1 Used : 0
    I2C2 Used : 0
    SPI Used : 0
    TC Used : 0
    WISHBONE Used : 0
    Dynamic Power (W) : 0.000000
    Static Power (W) : 0.000015
    Total Power (W) : 0.000015
    
    Other
    CLKDIV Used : 0
    CIBTEST Used : 0
    MCLK Used : 1
    SED Used : 0
    Dynamic Power (W) : 0.036611
    Static Power (W) : 0.028119
    Total Power (W) : 0.064730



  17. #17
    Advanced Member level 5
    Points: 22,696, Level: 36
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,345
    Helped
    959 / 959
    Points
    22,696
    Level
    36

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    The second block specify timing; the third specifies pin location, but only for two pins. You seem to be missing a bunch of constraints.

    Read the user manual about how to specify constraints.



    •   AltAdvertisment

        
       

  18. #18
    Newbie level 5
    Points: 57, Level: 1

    Join Date
    Mar 2019
    Posts
    9
    Helped
    0 / 0
    Points
    57
    Level
    1

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by barry View Post
    The second block specify timing; the third specifies pin location, but only for two pins. You seem to be missing a bunch of constraints.
    my design only has 2 outputs(uart clock and uart data), everything else is supposed to be internal.

    Quote Originally Posted by barry View Post
    Read the user manual about how to specify constraints.
    thanks, but aren't constraints more for optimization? either way I reading lattice's Lattice Diamond Tutorial and Lattice Synthesis Engine for
    Diamond User Guide



  19. #19
    Advanced Member level 5
    Points: 22,696, Level: 36
    barry's Avatar
    Join Date
    Mar 2005
    Location
    California, USA
    Posts
    4,345
    Helped
    959 / 959
    Points
    22,696
    Level
    36

    Re: FPGA synthesizes and simulates correctly but doesnt work on hardware

    Quote Originally Posted by kiyoshi7 View Post
    thanks, but aren't constraints more for optimization?
    Absolutely not. If you don’t tell the tool what pins to use, it will put them anywhere it likes. If you don’t tell what the operating speed is, it might work. Or it might not. Or it might work sometimes.



--[[ ]]--