Cesar0182
Member level 5
Greetings ... comment I am trying to create a project in vhdl from a tcl script in Vivado 2017.3, but I have problems when adding a source file, apparently it contains valid code lines only in vhdl 2008, therefore it is generating following errors.
This error refers to the following lines, valid only in vhdl 2008.
I would also like to mention that the previous lines of code were translated from the following lines in verilog.
Can someone please help me with this problem, thanks in advance.
I also attach the tcl script that I am using (in line 78 I add g1_applic_top_vhdl.vhd)
Code:
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Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 660.898 ; gain = 0.000
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ERROR: [Synth 8-995] hotlink_sdma_base is illegal in an expression [C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4_02_IEA/fpgas/g1/build/src/g1_applic_top_vhdl.vhd:30]
ERROR: [Synth 8-944] 0 definitions of operator "sll" match here [C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4_02_IEA/fpgas/g1/build/src/g1_applic_top_vhdl.vhd:30]
ERROR: [Synth 8-4696] default expression of interface object is not globally static [C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4_02_IEA/fpgas/g1/build/src/g1_applic_top_vhdl.vhd:30]
ERROR: [Synth 8-995] hotlink_sdma_base is illegal in an expression [C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4_02_IEA/fpgas/g1/build/src/g1_applic_top_vhdl.vhd:31]
ERROR: [Synth 8-944] 0 definitions of operator "sll" match here [C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4_02_IEA/fpgas/g1/build/src/g1_applic_top_vhdl.vhd:31]
ERROR: [Synth 8-4696] default expression of interface object is not globally static [C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4_02_IEA/fpgas/g1/build/src/g1_applic_top_vhdl.vhd:31]
ERROR: [Synth 8-955] hotlink_sdma_base cannot be used within its own interface list [C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4_02_IEA/fpgas/g1/build/src/g1_applic_top_vhdl.vhd:29]
INFO: [Synth 8-2810] unit g1_applic_top_vhdl ignored due to previous errors [C:/ProgramData/Teradyne/FPGA/VivadoProjects/RSBsdApp0x3020Revid_0x4_02_IEA/fpgas/g1/build/src/g1_applic_top_vhdl.vhd:27]
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Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 660.898 ; gain = 0.000
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RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 19 Warnings, 0 Critical Warnings and 8 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for detailsThis error refers to the following lines, valid only in vhdl 2008.
Code:
entity g1_applic_top_vhdl is
GENERIC (
Hotlink_SDMA_Base : integer := 0;
used_engine_mask : std_logic_vector(31 downto 0) := (X"000000FF" SLL Hotlink_SDMA_Base) OR '0';
used_wbus_chan_mask : std_logic_vector(25 downto 0) := ("00000000000000000011111111" SLL Hotlink_SDMA_Base) OR '0'
);
PORT (
...
);
end g1_applic_top_vhdl;
architecture Behavioral of g1_applic_top_vhdl is
begin
...
hotlink_ta_d <= OR ota_hotlink;
...
end Behavioral ;I would also like to mention that the previous lines of code were translated from the following lines in verilog.
Code:
parameter Hotlink_SDMA_Base = 0; // Define the first SDMA engine used by HOTLINK instance 0.
parameter [31:0] used_engine_mask = 8'hff << Hotlink_SDMA_Base | 1'b0; // Set 8 bits = 4 Hotlink ports * 2 engines
arameter [25:0] used_wbus_chan_mask = 8'hff << Hotlink_SDMA_Base | 1'b0; // Set 8 bits = 4 Hotlink ports * 2 wbus_chans
wire hotlink_ta_d = | ota_hotlink;Can someone please help me with this problem, thanks in advance.
I also attach the tcl script that I am using (in line 78 I add g1_applic_top_vhdl.vhd)
