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Input common mode simulation for the fully differential amplifer

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Junus2012

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Dear friends,

I know how to simulate the input common mode range of the amplifier by connecting it as a buffer and sweeping the input and monitoring the output voltage, the input common mode range will be then defined by the linear region from the output graph.

Now I am designing fully differential amplifier but I am not sure how to simulate the Input common mode range of it,

I would appreciate your help
Thank you very much
 

how about sweeping Vin from 0 to Vdd and monitor the drain currents of the input transistors, M1 and M2? we should expect that at Vin,cm=Vgs1,2+Vdsat3, Id1,2=Id3/2 which marks the lower vin,cm limit.

assad.JPG
 
thank you rmandu

by this simulation you will know the lower limit of the ICMR, what about the upper limit ?

let us considering the fully differential amplifier based on folded cascode topology
 

assad.JPG

at node X, Vx= Vdd-vsd = vdd-vsg+|Vthp|
for M1/M2 to stay in saturation Vin,cm<Vx+Vthn or Vin,cm<Vdd-Vsg+|vthp|+Vthn.
upper limit of Vcommon mode input can actually reach Vdd.
The same is true for PMOS inputs where Vin,cm for PMOS inputs can reach ground.

edit
I think to verify this in simulations the transconductance of M1/M2 can be monitored, since at triode
region gm deteriorates.
 
Last edited:

Thank you very much rmanalo for your help, hope to see you in my other posts
 

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