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LT3800 at > 10A output current

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ArticCynda

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Hi all,

I need a compact 48V to 12V buck regulator with high output current (40A). I thought of using the LT3800 as controller, and 2 Toshiba TPH2R608N N-channel MOSFETs in a synchronous push-pull stage.

All the calculations in the LT3800 datasheet however seem to suggest the maximum feasible output current is 10A, but being a novice in high power design, I don't see where this limitation comes from as long as the switches can handle the current (and reducing shunt resistor from 15 mOhm to 4 mOhm). My application doesn't care much about ripple on the output rail.

If someone could give me a hint, I'd be very grateful!
 

... as the switches can handle the current (and reducing shunt resistor from 15 mOhm to 4 mOhm). ...

And you follow all of the requirements and limitations of the control IC.
I suggest you pay extra attention to the drive capabilities of the IC, such as gate drive and high side voltage.
 

I don't see how the current through the MOSFETs/inductor/shunt resistor would affect gate drive or high side voltage, could you elaborate on what you mean?
 

Is there any reason you're designing your own? Any special requirements? While most controllers will probably be fine for most applications differences in control impact the end result in terms of transient performance, current limiting, stability etc.

Parametric search is pretty key here. 48V to 12V is slightly uncommon but there are still many off-the=shelf solutions such as this:
https://www.digikey.com/product-det...s-inc/I6A4W020A033V-001-R/285-2503-ND/5878834

I went straight for 10A but probably looking for 2 or 3 smaller parallelable modules will open up more possibilities....yes, such as this:
LTM8064
 

Available gate driver current can be an issue, the 10 A specification shall give an idea of useful application range. The selected Toshiba MOSFET is still meeting the Qg,max 180 µC specification in the datasheet, you should check if you achieve sufficient rdson at 8V Vgs and if the conduction loses of the low side transistor aren't too high.
 

In BJT switched drivers the current gain in each stage is limited by the reduction in hFE = 5% ~ 10% of rated when near Vce=Vce(sat) for low Rce losses where Pd=I²*Rce(sat) Where Rce= Vce(sat)/Ice based on tables in a datasheet and limited by the Vce vs Ice SOA power curves and heatsink. This results in an effective
current gain of 10 to 20 stage or 100 to 400 in a Darlington and high power switches may have 3 or 4 stages with many devices in parallel on the last stage.

In FETs it is different and greatly depends on the capacitance load and Ic=CdV/dt and thus CMOS switches increase current with frequency and again power dissipation increases with I² rates so C loads effectively increase losses by C².

The other characteristic about FETs is each similar FET family, the RdsOn times Qg is relatively constant so that as Rds specs are reduced capacitance increases for Qg, Ciss, Coss specs increase. ( This is true for all diodes (C@0V vs Rs at max current)) As I was saying at the start about BJT current gain stages the R switch stages need to be watched. While 2000:1 RdsOn ratios in cascaded stages might be best case for low power designs, I have seen some with as low as 20:1 RdsOn in kW power designs.

You can imagine that a CD4000 high voltage logic 300 Ohm switch cannot drive a 1 mΩ Toshiba FET very fast in frequency because of large Rg and Ciss rise time loading effects on 300 Ohm high voltage CMOS logic.



My observations are that the FET characteristics also follow a similar but higher ratio as BJT's for current gain except for a different reason. What that ratio is, I believe depends on peak/RMS current ratio in the design, thermal design and specs for efficiency and range of current needed e.g. Max:min.vs efficiency

It is also normal for Ipk rating on the FET selection to be at least 5x the Irms of a good DC-DC design.

I see that in your choice with wanting 40A RMS out and a FET with 500A pk pulse current rating but rated RdsOn of 2.6mΩ at 50A @Vgs=10V seems reasonable.
The Gate is 1.5Ω max , Ciss is 9000pF max.with a Qg =72nC @ VDD ≈ 37.5 V, VGS = 10 V, ID = 50 A at 25'C while RdsOn rises with temp.

Your shunt resistor choice of 4mΩ is now greater than the RdsOn making it lossier and dissipating 10 Watts = (Pd=I²*Rs) at 50A avg and much more at peak current which is a problem. The reverse current sense comparator has a 150mV threshold may be relevant with the clamp diode Rs choice.

From the LT3800 performance curve on p4 of ICC Current Limit vs Temperature, it is 50mA ~ 60'C
So when does the LT3800 overheat or shutdown from current limit vs temp? The IC current limit has a negative slope is about -0.8mA/'C rise in Temp.

from the datasheet the VCC 8V output voltage can be used to determine QG. Required drive current for a given FET follows the simple relation:

IGATE = Qg(8V) • fo
( this makes sense as Ic=CdV/dt=dQ*f) thus Ic=72nC * 200kHz = 14.4mA
This seems reasonable. so far


Next problem is parasitic inductance
.Next issues will be parasitic inductance , DCR and Cin ESR with your layout at 0.5~1nH/mm in your PCB track choices at 5A/ns more or less rise times. so V=LdI/dt for a 1mm trace can be V=1nH*5A/ns= 5V
 

Regarding: I suggest you pay extra attention to the drive capabilities of the IC, such as gate drive and high side voltage.

The control IC has some gate drive capability. Each transistor has some gate drive so you can turn it on. You need to make sure the IC can drive the transistors you pick, otherwise you'll need a driver IC.
Likewise, the control IC has some maximum operating voltage. The high gate drive has to work within that range, or you'll need some extra gate drive circuit.
 

Re: LT3800 at > 10A output current

Hi
Here is some stuff on paralleled Bucks to help you...paralleling can be good for high current.

- - - Updated - - -

i also tried to attach more stuff for you, but it is hesitating due to the size.
If you wish, i will send you the stuff on email via google drive.
Pleas email andymassey22@gmail.com if you want the entire SMPS course (its free)
 

Attachments

  • Low Vout high current SMPS.zip
    136.2 KB · Views: 64

Interleaved converters can be a variation on parallel converters. Gating is staggered so as to spread the burden. Multiple inductors might be less bulky, less heavy, less expensive, as compared to one large inductor.
The inductors carry fewer Amperes each, presumably with less heating.

Example circuit, 3 interleaved buck converters. For ease of simulation they are driven in rotation by a 4017 IC (decade counter). Each duty cycle is 33 percent.


interleaved 3 buck converters driven by 4017 48v to 13v 43A.png

Parasitic resistance needs to very low. Merely 1/10 ohm carrying 40A causes a drop of 4 volts in the system.

A simulation with 4 interleaved converters (each 25% duty cycle) was unable to reach 12V 40A. To achieve that their clock cycles need to be longer than 25 percent, which means they must overlap and must be adjustable.
 

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