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3 phase 400Vac 5000W Full bridge converter power factor correction Buck or Boost type

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rxpu

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I have a 3 phase 400Vac supply rectified to 540VDC.


A full bridge phase shift converter converts the 540VDC @10A to 10Vdc @500A.



I try to figure out a power factor correction frontend for this converter.(using UCC29910 from TI)


The main question is : Buck or Boost?



I tend to use the buck topology rather than the populated Boost



My Reasons for Buck Topolgy:



Option 1

-No Inrush current. (soft start is possible)

-Possiblity to step down the 540VDC to 320VDC through PFC preregulator so that the phase shift converter design will be simpler and cheaper. Semiconductor Voltage rating is 600V instead 1200V which saves cost.



Option 2

There is also a possiblity that I convert 540VDC to 48VDC through the Power factor correction converter. The semiconductor Voltage rating reduces to 100V instead of 1200V which gives me the possibility to reduce semiconductor cost and increase the frequency and reduce system volume.



Any recommendation between Option 1 and Option 2 , Or maybe some remarks for Boost Topolgy? (Boost topolgy has some drawbacks in my case. The Bus voltage must be 40-50V greater than 540VDC bus which makes the design and implementation harder and cost of the semiconductors increases. The inrush current is also a problem for boost topolgy which needs extra effort and circuit and increase costs.



Thanks for your input.
 

Are you interested in PFC, or harmonic distortion?

If you haven't read this, I recommend reading it:
https://www.ti.com/seclit/ml/slup264/slup264.pdf

You have a three phase line, which means three PFC units, by phase pairs (AB, AC, BC).

Suggested reading:
https://www.st.com/en/applications/...nverters/pfc-converter-three-phase-input.html
https://www.eevblog.com/forum/projects/3-phase-pfc-why-so-hard/

Option 2:
You have a 540 V rectified line. I do not see how you only need 100 V semiconductors.
 
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Boost topolgy has some drawbacks in my case. The Bus voltage must be 40-50V greater than 540VDC bus

It's not clear if you wish to produce 580-590v?

In any case here is a way to arrange a buck-boost converter so it adds 40-50V above the 540v supply rail.

buck-boost clk-driven adds 50v above 540v supply rail.png

The boost type adds the supply voltage to whatever comes through the inductor.
The buck-boost generates voltage only via the inductor.
If this does not answer the question, simply disregard my post.
 
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I want to avoid the boost topology. Because the PFC output Voltage should be adjusted between 590VDC-600VDC.

If I have buck topology. I may simultaneously step down the 540VDC to 320VDC and get power factor correction through the PFC preregulator (UCC29910). So the cascading converter is based on 600V semiconductors and one row of 400V capacitors instead of 1200V semiconductors and 2xseries connected 400V capacitors+ balancing resistors.

My main concern is, if I look at the IC, It samples the rectified input voltage (after the smoothening capacitor) and the PFC output Voltage. If the capacitor after the B4 bridge a small EMC filter capacitor then the IC will have the possibility to sample the phases of the Ac line. But if it is a big smoothening capacitor the phase information is lost. Because the Bus voltage ripple will be less.

As my understanding the IC should have information abaout the phase of the voltage so that it can shape the form of the input current with respect to the phase of the voltage.

But in my case I am not sure if I can use this IC *after* the B6 bridge. Because the IC will see the phase at 300Hz and 60 degree apart. And the grooves of the Ac line ripple is not so deep as in the 230Vac.

Any ideas to use 1 PFC control IC after the rectified 3 phase AC line instead of 3 seperate PFC for each phase?
 

Option 2 : If I use the PFC preregulator as a step doen (buck) converter, I may adjust the PFC output voltage to a much lower level. ex: 48VDC. So that the cascading converter needs semiconductors and capacitorsa with lower voltage ratings.

My main problem is (as I stated above) I have 3 phases instead 1. The IC should have some phase information to adjust the form and phase of the current respect to the voltage.

This is the picture of the PFC control schematics: (buck)

PFC-Buck.jpg

As you see the IC samples the input Voltage after the rectifier. There is also a capacitor. If it is a smoothening capacitor the phase information is lost. But I think that it is a small EMC film capacitor so that the ic can sample the phase information even after the rectifier. But I am not %100 sure.

The main question is : Can this IC and its algortihm regulate a PFC for a three phase line?

Should I use 3 seperate B4 bridge and Ics to get proper PFC regulation?
 

Another schematic where it is clear to see that the IC samples only the DC Bus.
It is really unclear how the synchronizes the Voltage and current without knowing the phase position of the input line.
(I tend to think that the capacitor after the rectifier is really small so that the ac line and its grooves are sampled by the IC even after the rectification.)

PFC-Buck-Lowside.png
 

Instead of focusing on measurement and control problems, you should first choose a converter topology that is able to work as three phase buck pfc. The yet discussed topologies can't.

There are examples in literature like the swiss rectifier which can be seen as a current bus complement of the vienna rectifier.
 
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Dear FvM,

I am trying to use commercially available ICs for the PFC stage. I have constructed a topology by using 3x UCC29910. I rectified L1 and L2 got 540VDC @50hz, L2 and L3 and L3 nad L1. After each PFC stage I added 3 seperate isolated phase shift full bridge converter. Finally I combined the outputs of each converter .

I send a sketch of the topolgy. What do you think abaout it?. I want to construct the input network without the neutral line. Only using L1,L2 nad L3. Each PFC using buck topolgy will try to correct between correspanding phases.

Any ideas if it works?

PFC-Buck-seperate-3Phase.jpg
 

Yes, three separate DC/DC isolators is of course an option. But you need relative large DC bus capacitors if you don't want to design the DC/DC converters for double peak power.
 

Yes, three separate DC/DC isolators is of course an option. But you need relative large DC bus capacitors if you don't want to design the DC/DC converters for double peak power.

I have seperated the @5000W converter into 3 seperate 1700W converters.

I hope 0.4uF/watt will be sufficient. So each converter has 2 paralel 330uF(400V) capacitors. Total 660uF per converter.

The PFC buck stage reduces the bus voltage to a level where I get rid of series connected high voltage capacitors and balancing resistors.this reduces also the cost of the capacitors.

What do you mean by double peak power?

Do you mean that I must reserve some margin for synchronisation and paralelisation of the seperate converters?
 

What do you mean by double peak power?

The PFC is supplying 100 Hz pulsating power to the DC bus, peak power is double the average power. If the DC/DC is sinking constant 1700 W from the DC bus, you get about 70 V ripple with 660 µF capacitors. This can work if the DC/DC achieves respective voltage regulation.
 

Comments about the schemativ in post #8:

1. There should be no filter capacitor after the rectifier. The pfc circuit must use the unfiltered rectified voltage.

2. For a buck pfc, there is a relationship between power factor and output voltage.
When the input voltage rises from zero, the buck pfc can't increase the input current until the input voltage is higher than the output voltage.
I think the current waveform (and power factor) will be bad for a 400VAC input and 350VDC output buck pfc.
I think the output voltage should be much lower to get an acceptable power factor for a 2000W buck pfc.
 

The PFC is supplying 100 Hz pulsating power to the DC bus, peak power is double the average power. If the DC/DC is sinking constant 1700 W from the DC bus, you get about 70 V ripple with 660 µF capacitors. This can work if the DC/DC achieves respective voltage regulation.

Thank you for the detailed explanation. I see that the low frequency ripple can only be smoothened by a capacitor at the PFC output or by a tight and fast regulation scheme of the cascading converter. 70V ripple for 350VDC input voltage means 2V ripple for 10V output voltage. This must be the downside of seperating the 300hz bridge to 3 seperate 100Hz bridges to simplify the design and to be able to use the populated PFC ICs. I also investigate bridgeless topologies which I saw some examples that are implemented with commercially available PFC ICs like UCC28070 or NIC1653.
 

Comments about the schemativ in post #8:

1. There should be no filter capacitor after the rectifier. The pfc circuit must use the unfiltered rectified voltage.

2. For a buck pfc, there is a relationship between power factor and output voltage.
When the input voltage rises from zero, the buck pfc can't increase the input current until the input voltage is higher than the output voltage.
I think the current waveform (and power factor) will be bad for a 400VAC input and 350VDC output buck pfc.
I think the output voltage should be much lower to get an acceptable power factor for a 2000W buck pfc.

Yes , I also noticed in the application note that this capacitor is a very small capacitor in nF range.

Regarding the output voltage, I also calculated a second scenario where the output voltage of the PFC is 48VDC.

But there is a problem. the power loss of the PFC buck converter is very huge. Stepping down 540VDC to 48VDC @1700W through a half bridge (or a mosfet + lower side a ultrafast recovery diode) have 40 amps of circulating current. This means a minmum of 150-200W power loss for the PFC semiconductors.

I may use expensive SiC mosfets to lower the power loss on the PFC stage. But even then, the power loss is not drastically lower.

If I had the possibility to achieve better efficincy for the PFC-Buck stage for 48VDC output voltage, it would be possible to use semiconductors with 100V breakdown voltage and much more important it would be possible to go beyond 400-500kHZ switching frequencies for the cascading phase shift converter.

Any ideas to get more power efficiency for a PFC-Buck output voltage of 48VDC.

Or if it is not possible what do you think that the optimum output voltage of the PFC stage should be for 400Vac (540VDC) input.

what may be the sweet spot? 150V? 200V? 250V?

Thanks for your input.
 

If I had the possibility to achieve better efficincy for the PFC-Buck stage for 48VDC output voltage, it would be possible to use semiconductors with 100V breakdown voltage and much more important it would be possible to go beyond 400-500kHZ switching frequencies for the cascading phase shift converter.

I don't understand this. Why would 100V breakdown be enough for a 48V output buck pfc?
I think the semiconductors must withstand almost the same voltage as for a boost pfc.
 

I don't understand this. Why would 100V breakdown be enough for a 48V output buck pfc?
I think the semiconductors must withstand almost the same voltage as for a boost pfc.

The input of the PFC-Buck is 540VDC. And the regulated PFC Buck converter output is 48VDC. The difference stays on the PFC-Buck inductor, the more energy you store on the buck inductor the more effective is the power factor correction.

The cascading (following) converter (in our case the full bridge phase shift converter) after the PFC preregulator sees only the output voltage of the PFC-Buck stage. And if it is 48VDC, it will be enough to use semiconductors (mosfets) that hava a breakdown voltage of 100V.
 

The input of the PFC-Buck is 540VDC. And the regulated PFC Buck converter output is 48VDC. The difference stays on the PFC-Buck inductor, the more energy you store on the buck inductor the more effective is the power factor correction.

Sorry, that's not right. The inductor has 0 V at start up, so all of the rectified bus must be on the semiconductor.
If the inductor does carry all of that voltage, as you suggest, the change in voltage across the inductor during charge or discharge has to be limited to less than 48V. Not a good limitation if you want efficiency or PFC or both.

Back in post #7, FvM wrote "There are examples in literature like the swiss rectifier which can be seen as a current bus complement of the vienna rectifier. "
I suggest you look up the Swiss rectifier - a quick look at an IEEE paper shows that it takes the rectified three phase and performs power factor correction sufficiently high to have good harmonic content.
 

Sorry, that's not right. The inductor has 0 V at start up, so all of the rectified bus must be on the semiconductor.
If the inductor does carry all of that voltage, as you suggest, the change in voltage across the inductor during charge or discharge has to be limited to less than 48V. Not a good limitation if you want efficiency or PFC or both.

Back in post #7, FvM wrote "There are examples in literature like the swiss rectifier which can be seen as a current bus complement of the vienna rectifier. "
I suggest you look up the Swiss rectifier - a quick look at an IEEE paper shows that it takes the rectified three phase and performs power factor correction sufficiently high to have good harmonic content.

Just to be clear, the semicondcutor voltage rating of the PFC-Buck stage should be 1200V. The switch is respecting the whole 540VDC.

We were talking abaout the semiconductor voltaga rating of the cascading (following) converter. In this case , if the PFC-Buck preregulator regultes its output as 48VDC, then the cascading converter needs semiconductors with a voltage rating of 100V (with respect to 48VDC).

I have investigated the swiss rectifier. It is the most perfect fit from the technical aspect. But it needs too much engineering effort and time. I am trying to find a solution with commercially available solutions from TI or Onsemi. (Ucc29910 etc.).

Ich have find some documentation that some PFC controller ICs from texas and onsemi (example: UCC28070) is constructed to function as bridgeless PFC regulators. They replace part of the rectifier diodes in the bridge.

The swiss rectifier needs also Rectifier Bridge + 6 back to back switches. It means it needs much more effort not only for software but also for the hardware implementation. (gate drives , etc.). But I agree that the vienna and swiss rectifiers are the best solutions from the technical aspect.

- - - Updated - - -

I have calculated the trade off between output voltage and PFC power dissipation:

Formule for condcution angle:

Con_angle= 2.arccos(Voutput/Vinput)x180/pi

Input: 400Vac (540VDC)

Output Cond. Angle (%) (degree) Power Diss.(for Total 3x1700W=5100W)

350VDC %55 99 degree 48.6W Eff. %99

200VDC %75 136 degree 60W Eff. %98.8

150VDC %82 147 degree 78W Eff. %98.5

100VDC %88 158 degree 104W Eff. %97.9

80VDC %90 163 degree 123W Eff. %97.5

60VDC %93 167 degree 156W Eff. %96.9

48VDC %94.3 170 degree 186W Eff. %96.3

What do you think abaout the trade off. Which PFC output voltage is the optimum regarding the conduction angle and the efficiency?

I have also some uncertainity for lower output voltages.

For example: 540VDC input and 48VDC. The IC must work between a duty cycle value of 0 and 0.1. This band is really narrow.

The whole output regulation should be done varying the duty cycle between %0 and %10. May this be a limitation for the quality of the reguation.

According to datasheet 230Vac (320VDC) input and 75VDC output is a practical implementation. But in our case the step down ratio is much less.

Any ideas?
 

Lower PFC output voltage corresponds to higher output current, higher semiconductor losses etc. The effect doesn't seem to be considered in your calculations. Higher buck voltage rates than 4:1 are generally undesirable.
 
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Lower PFC output voltage corresponds to higher output current, higher semiconductor losses etc. The effect doesn't seem to be considered in your calculations. Higher buck voltage rates than 4:1 are generally undesirable.

I also asked a similar question on TI forum. TI recommended using the boost PFC for industrial use. (explanation from TI see below)

What do you think abaout the boost topology?. My DC bus should be amplified at least to 590-600VDC. What would you do if you were the designer:

Option 1: PFC-boost. Dc Bus amplified to 600VDC .3 PFC converter + 3 Phase shift converter with 1200V Sic Mosfets + 1200V SOI isolated gate drivers.
I think I also need 3 seperate PFC-boost converter so that they can synchronise with the AC-line. Following is an example of boost controller.

https://www.ti.com/lit/ds/symlink/ucc28070.pdf


Option 2: PFC-buck. DC bus stepped down to 150VDC. 3 PFC converters + 3 isolated phase shift converters. 200V mosfets+600V half bridge mosfet drivers, higher frequency, smaller volume. Cheaper. Much simpler design than the 1200V design. No more than (1:4) reduction ratio is satisfied.
I also noticed that if we combine 3 seperate isolated converters from each phase at the output, we also combine 3 120 degree shifted 100Hz line, so that we gain again the 300Hz ripple which we have seperated at the beginning. In this manner the capacitor value may decrease if these 3 120 degree shifted 100hz converters are combined as superposition at the output. Would you agree with this?





TIs answer:
_______________________________________________________________
It is not recommended that you use a buck pfc stage for a high power and high voltage application such as you describe above.
The reason is this topology is very sensitive to failure of the semiconductor switches during a line surge or lightning strike.
It is recommended that you use a boost pfc stage followed by a high voltage phase shifted full bridge.
_______________________________________________________________
 

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