Negative Slack / Report Analysis

std_match said:

I think you should show us the complete FIFO source code. We can only guess why you have these problems. We don't know how many clock domains you have, or which clock domain executes the small code snippet you have shown.
It is not clear if you really need the "diff" value. You don't need it to create empty/full flags.
If you are using Xilinx, you will get the fastest FIFO by using the block RAM primitive and tell it to be a FIFO. The block RAMs have integrated FIFO logic.

Click to expand...

first of all I'm using Lattice Radiant

everything works as it is basically, the main question is just about the floorplanning and if I'm supposed to be able to influence the floorplanning.

for example The current synthesis result was:
Logic Level 3
Delay Ratio: 82.2% (route), 17.8% (logic)

there are 3 "NET DELAY" items in the Datapath
4.066ns, 2.768ns, 3.775ns

https://pasteboard.co/I5wtYqQ.png

That path is for calculating the full fifo of the first input.

the purple blocks are the EBRs I'm trying to have 2 input blocks with 100mhz each, I would like to have eg. input block A on the top left side and input block B on the left bottom side of the floorplan... however I cannot figure out how that's possible.

The floorplan has the option "CREATE REGION" which I can span over the desired area.
I have tried to add following attributes into the fifo instance (hoping to keep all the logic within a defined area, however the only thing I was able to do is to "prohibit" the use of the other available EBRs).

Groupname is passed as an argument to the instance which is instantiated 2 times in the top module.

attribute HGROUP: string;
attribute HGROUP of rtl : architecture is GROUPNAME;
attribute syn_hier: string;
attribute syn_hier of rtl: architecture is GROUPNAME;

The second option in the floorplan would be "CREATE GROUP BBOX" but that will only allow me to put 32 elements into it.

the inputs are actually directly next to the EBRs, however the synthesis tool mixes EBRs for each input from the top and bottom side.
eg. 4 top EBRs and 4 bottom EBRs for Input 1 and the other 4 EBRs from top/bottom for Input 2.

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https://pasteboard.co/I5wz73W.png

such a placement looks like absolute nonsense to me, the right bottom element, why is it that isolated?

I'm just trying to understand why it's so bad...

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"Properly applied, design floorplanning not only preserves but also improves design performance. You can use floorplanning to place modules, entities, or any group of logic into regions in a device’s floorplan. Because floorplanning assignments can be hierarchical, you can have more control over the placement and performance of modules and groups of modules. For example, the following PAR report shows a path’s detail with over 80% routing delay. Floorplanning might be able to bring the registers closer:"

That's what lattice writes in a design planning document (but that document was written for Lattice Diamond which is probably more mature since it's older), however Lattice Radiant doesn't seem to offer proper techniques to do some realistic floorplanning.
Radiant is relatively new, does anyone have more experience with it?

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To what it's worth I have moved back from Lattice Radiant to IceCube2 .. it's giving totally different placement results (so I'm at the beginning of my placement investigation again).

my final solution was to decrease the memory. I'm sure it could be done with all the memory onboard but interconnecting blocks from different banks introduces very hard to meet delays. Routing delays were 80%+ Logic Level 2-3.
If I would design a real chip I would have isolated the blocks and interconnected them via well defined interfaces -- that is especially what is not (yet) possible with this part due to the synthesis/place and route tools (even though there are enough LUTs available and interconnecting paths). (This is based on my current assumption, please correct me if I'm wrong).