P mosfet source and drain short

I am trying to use P Mosfet as a switch whose gate is controlled by the N MOS. The schematic is shown in the image.



I was testing the circuit loading sections. Everything seemed to work fine.

I had not used a capacitor at the source side till then but once I load those (circled in red), the drain and source of the mosfet started showing short and the Vdrain was always at 24V.

I was providing a TTL pulse of 500ms at TP8.

I am not sure why that was happening. Irrespective of if I load caps (Circled in red) at source of P Mos r not, it will anyways be at 24V and should work fine.

What am I missing here?

Hi,

I personally don't like the "none/low source capacitor" idea.

Imagine it as water reservoir: (referring to your schematic values)
* the reservoir has a volume of 2000 liters
* you want to fill containers with 4000 liters.
The result will be that you quickly can fill only up to 33% .. then there is equal level in both containers .... and you need to wait for the 67% water coming from the supply water pipe..

In other words ... with fast switching times you can expect that the input voltage will intermediately may drop down to 8V only.

Thus I rather recommend a 6000uF reservior on the source side and only a 100uF at the load side.
(For sure in details depends on the application requirements)
It will quickly charge to 98% ...
(Intermediate voltage drop down to 23.6V)

Now when you switch ON a capacitor with a transistor ... there will be power dissipation in the transistor.
This dissipated energy mainly depends on supply voltage (squared) and output capacitor ... but not on switching time.
So with a smaller output capacitor there will be smaller dissipated energy --> less stress in the transistor.

Additionally you may "stretch" the time ... this means that the energy is spread in time. This gives a smaller peak in dissipated power, which means again less stress in the transistor.

A good solution my be to add a 1uF capacitor from 24V_MECH to gate of U1.
This reduces output voltage rise rate to about 3V/ms.
And thus it reduces charging current for the output capacitors.
The output will be ON within 10ms.

For sure you may play around with other part values. Easiest way is to use a simulation software.
Mind to use realistic power supply impedance. ... and overcurrent behaviour.

Klaus

Added: I think that values of R5 and C9 are not useful. Tell us what you want to achieve.

No transistor spec given, but I presume the circuit will easily exceed the transistor safe operation area.

ideally I wouldnt even use a cap at the source of P Mos

Imagine the following scenario

24V --> electrolytic cap --> DC to DC

24V --> ON/OFF Mosfet Control to load and that requires more CAPS (Output CAPS at drain)

If both of these are needed

The electrolytic cap used on DC to DC (C1, C2 in this example) will have effect on P MOSFET operation that is used as a switch for some load driving.

Hence was checking for all possible issues.

- - - Updated - - -

FvM said:

No transistor spec given, but I presume the circuit will easily exceed the transistor safe operation area.

Click to expand...

https://www.mouser.in/datasheet/2/408/TPC8129_datasheet_en_20140121-1150903.pdf

Link for the PMOS that I am using.

- - - Updated - - -

KlausST said:

Added: I think that values of R5 and C9 are not useful. Tell us what you want to achieve.

Click to expand...

Not Useful. R5 is shorted/0R and C9 as of now is NC

Hi,

ideally I wouldnt even use a cap at the source of P Mos

Click to expand...

This is the worst case you can do.

Klaus

KlausST said:

Hi,


This is the worst case you can do.

Klaus

Click to expand...

I am trying to use this.



As of now its working fine. (I am testing results only on CRO, no actual loads)

24_MECH will draw about 3 odd amps

and DC to DC will be designed for 2 or 3 amps

Hi,

I am trying to use this.

Click to expand...

This is exactly the opposite of my recommendation.

Funny ...

Klaus

KlausST said:

Hi,


This is exactly the opposite of my recommendation.

Funny ...

Klaus

Click to expand...

Don't mean to offend or miss ur suggestion. I did consider that too... But it dint help.

I was just trying various things and some any value of electrolytic cap at source of pmos seems to short drain and source.

I am still not sure why that's happening.

With this it just seemed to work...

Although I don't wish to use 2 diodes but I m unable to understand what is it that I m missing.

Hi,

I was just trying various things and some any value of electrolytic cap at source of pmos seems to short drain and source.

I am still not sure why that's happening.

Click to expand...

The answer is in post#3
The explanation and calculation is in post#2

I believe you that your solution is working.
It is working, because the input side (left of the MOSFET) now is weak .. and thus the peak current is low.
This results in intermittant voltage drop at the 24V side.
Depending on switching time and charge status of output capacitors .. I won´t be surprised if it drops to less than 8V.
This voltage drop may cause other devices connectod to the 24V supply to stop operation. ... and then restart.

(I´m doing mainly industrial electronics design. In this field it is a no-go if one device is switched ON it makes other devices - connected to the same supply - to stop working.)

This mistreating of the power supply is called a "dirty" solution.
But it´s your decision how you solve the problems.
I just want to inform you that you may expect problems - maybe in the future.

Klaus

The description is incomplete, we don't know the current deliverance of the DC power supply. Thus it's unclear if reducing the effective capacitance on the left transistor side reduces the transistor stress.

The post #1 circuit with 2 mF at the left and 5 mF at the right of the transistor will dissipate about 430 mJ in the transistor when switching it on, the value may be reduced by (unknown) capacitor ESR. The dissipated energy is most likely beyond SOA spec, which would explain the transistor damage.