Floorplanning example?

Hi,

can anyone recommend an FPGA Floorplanning example?
The best would be a bad example turning to something good after floorplanning iteration.

I just went through a software-approach of implementing a fifo in an FPGA and terribly failed (however what I have learned during that process was extremely good), the final "hardware"-thinking approach decreased not only the amount of luts but also, slack by 3/4th.
Something learning curve like that with floorplanning would be perfect... problem -> bad floorplanning (see how things get worse) -> good floorplanning (improving everything).

The best thing do is learn good coding techniques. The first step in improving design is improving the source code.
Its very difficult to see from floorplanning why something is good bad - as you need the routing information too, which isnt visualised.
Forget about floorplanning - think about learning to code better.

The only times I ever use floorplanning are for the following reasons

• Placer places primitives that connect directly to IO too far away from IO to meet IO timing constraints (I've seen this occur on all FPGA vendors tools over the years). In these instances tightening up the constraints sometimes doesn't work and/or makes other areas fail timing (all because you forced the placer to move that cell 1-2 ns closer to the pin, fyi doing so manually in whatever FPGA editor they have does meet timing)
• Need to leave an empty area for another block that you know will be inserted at a later time.
• Using partial reconfiguration.
• Forcing the design into specific regions because of a large number of clock domains and restrictions on how many clock can be in any given region.

I've never floorplanned a design in a modern FPGA technology outside those specific reasons. I used to have to hand place and hand route Xilinx 3000 series parts to get them to meet our clock frequency goals, but that is an extreme example of a poor annealing algorithm for placement.

can anyone recommend an FPGA Floorplanning example?
The best would be a bad example turning to something good after floorplanning iteration.

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As mentioned above by ads-ee, the chances of using floorplanning is very rare. Even if members here have such projects on their workstations, they would not be shared due to company confidential reasons.

I just went through a software-approach of implementing a fifo in an FPGA and terribly failed (however what I have learned during that process was extremely good), the final "hardware"-thinking approach decreased not only the amount of luts but also, slack by 3/4th.

Click to expand...

Probably you are working with some high-level synthesis (Xilinx HLS?) software.
If you have RTL knowledge, just customize that generated code such that it makes more sense.

dpaul said:

Probably you are working with some high-level synthesis (Xilinx HLS?) software.
If you have RTL knowledge, just customize that generated code such that it makes more sense.

Click to expand...

player80 mentions a software approach but that was strictly an issue (on a previous thread) with not understanding clock delays and approaching the interface design to an Intel dcfifo IP core as if everything happens in and orderly fashion (software sequential code) and will be done when you look at it a few lines of code later. They didn't actually try to code a FIFO from scratch or write it in HLS.