player80
Full Member level 2
Hi,
can anyone recommend an FPGA Floorplanning example?
The best would be a bad example turning to something good after floorplanning iteration.
I just went through a software-approach of implementing a fifo in an FPGA and terribly failed (however what I have learned during that process was extremely good), the final "hardware"-thinking approach decreased not only the amount of luts but also, slack by 3/4th.
Something learning curve like that with floorplanning would be perfect... problem -> bad floorplanning (see how things get worse) -> good floorplanning (improving everything).
can anyone recommend an FPGA Floorplanning example?
The best would be a bad example turning to something good after floorplanning iteration.
I just went through a software-approach of implementing a fifo in an FPGA and terribly failed (however what I have learned during that process was extremely good), the final "hardware"-thinking approach decreased not only the amount of luts but also, slack by 3/4th.
Something learning curve like that with floorplanning would be perfect... problem -> bad floorplanning (see how things get worse) -> good floorplanning (improving everything).