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[SOLVED] Can you help me with this Verilog to VHDL translation?

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Ironlord

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Hello.

I have this Verilog code which is working, and I would like to translate it to VHDL. I have tried but the VHDL design is not working when I synthetise it, but the VHDL works without problems.

VERILOG:
Code:
module entrada (
    input FPGA_CLK1_50,
    input reset,
    input [3:0] switches,
    output avl_irq,
    input  avl_read,
    output [3:0] avl_readdata
);

reg [3:0] cur_inputs;
reg [3:0] last_inputs;
wire [3:0] changed_inputs = cur_inputs ^ last_inputs;

reg irq;

assign avl_irq = irq;
assign avl_readdata = last_inputs;

always @(posedge FPGA_CLK1_50) begin
    if (reset) begin
        cur_inputs <= 4'd0;
        last_inputs <= 4'd0;
        irq <= 1'b0;
    end else begin
        cur_inputs <= switches;
        last_inputs <= cur_inputs;
        if (changed_inputs != 4'd0)
            irq <= 1'b1;
        else if (avl_read)
            irq <= 1'b0;
    end
end

endmodule

VHDL:
Code:
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;


ENTITY entrada IS
	PORT(
		FPGA_CLK1_50: IN STD_LOGIC;
		reset 		: IN STD_LOGIC;
		switches 	: IN STD_LOGIC_VECTOR(3 downto 0);
		avl_irq 		: OUT STD_LOGIC;
		avl_read		: IN STD_LOGIC;
		avl_readdata: OUT STD_LOGIC_VECTOR(3 downto 0)
	);
END entrada;


ARCHITECTURE MAIN of entrada IS

	signal cur_inputs : std_logic_vector(3 downto 0):="0000";
	signal last_inputs: std_logic_vector(3 downto 0):="0000";
	signal changed_inputs : std_logic_vector(3 downto 0):="0000";
	signal irq : std_logic:='0';
	
begin
	
	avl_irq<=irq;
	avl_readdata<=last_inputs;
	changed_inputs<=cur_inputs xor last_inputs;

	process(FPGA_CLK1_50)
	begin
		if(reset='0')then
			cur_inputs <= "0000";
			last_inputs <= "0000";
			irq <= '0';
		else
			cur_inputs<=switches;
			last_inputs<=cur_inputs;
			if(changed_inputs/="00000000")then
				irq<='1';
			elsif(avl_read='1')then
				irq<='0';
			end if;
		end if;
	end process;

end MAIN;

I don't know what am I doing wrong. Could anybody illustrate me?
 

Hi,

No error message?
No error description?

Klaus
 

Both synthesis are correct, but they are not doing the same thing when I program it on the FPGA.
As I am a newbye at Verilog, probably I messed up with something. Maybe the xor is not correct in VHDL or maybe I'm not doing it well with "changed_inputs" signal.

Also, I am not sure about reg and wire difference. Are both signals in VHDL?
 

Dear Ironlord,
I'm not known the verilog language but you have to pay attention on these two code lines:

cur_inputs<=switches;
last_inputs<=cur_inputs;

in VHDL you are defined cur_inputs and last_inputs as two signals. So the value of cur_inputs will be update only on the next rising edge of clock and not immediately.
If you wolud use its value immediately cur_inputs must be declared as variable inside the process.

I hope that it is useful

Regards
 

Also, I am not sure about reg and wire difference. Are both signals in VHDL?
Why are you doing this?

As I am a newbye at Verilog, probably I messed up with something.
Then you must stick to one and learn it thoroughly.

Your VHDL process is messed up.

Code:
	process(FPGA_CLK1_50)
	begin
          if rising_edge(FPGA_CLK1_50) then

            -- Your logic here
          
          end if;
	end process;
 
Yes, I forgot this line as I was doing a literal translation, but it is not the only problem.

About your question...
There's a lot of documentation written with Verilog examples, so I want to learn to understand it and I do it translating it to VHDL.
it would be easy to copy some Verilog code, paste it in the project and accept it as it is, but I want to understand how it works and how it would be in VHDL.

I have done the same with other Verilog codes, but I can't see what's wrong with this one.
 

If something works in one language, then you are always safer having it in the original language. Have two copies of the same code doubles the chances of bugs, as you have two copies of the same thing to maintain (plus translation bugs as you're finding). Its much better to learn one language and you'll find you should be able to read the others.

Translating code is not much use IMO.
 

If something works in one language, then you are always safer having it in the original language. Have two copies of the same code doubles the chances of bugs, as you have two copies of the same thing to maintain (plus translation bugs as you're finding). Its much better to learn one language and you'll find you should be able to read the others.

Translating code is not much use IMO.

I agree with that. I am a VHDL coder.
Anyway, that's an VHDL example I followed in order to generate IRQ interrupts. I achieved to send IRQs from FPGA to HPS and I would like to make more complex designs. As I am an VHDL coder, I would like to translate it in order to build in VHDL over that design. When I began learning HDL, i wasn't able to understand Verilog, now I am improving my skills, but I still thinking I should learn both languages.
 

Reset polarity also changed between verilog an vhdl codes

- - - Updated - - -

The reset in Verilog is active high, you wrote it as an active low reset in VHDL.
 
What tool do you use for synthesis? Does it support both languages? If so, then you can instantiate Verilog modules inside VHDL wrappers and vice versa.
 

It must be something more wrong.
I added the "if((rising_edge(FPGA_CLK1_50)) then" sentence and changed the reset to "if(reset='1')then, but still not working.

I don't think I can wrap it because I use this module as a Qsys IP Core. I'm working on Quartus and this project is to interface the FPGA interrupts with the ARM processor. I'm catching the interrupts in a Linux Kernel module, which works as a driver. It works when I program it with the Verilog code, but I want to make it in VHDL.

EDIT:

Sometimes I am an idiot...
I was comparing a 4-bits vector with a 8-bits vector, so it never entered in the sentence:
Code:
signal changed_inputs : std_logic_vector([B][COLOR="#FF0000"]3 downto 0[/COLOR][/B]):="[B][COLOR="#FF0000"]0000[/COLOR][/B]";
if(changed_inputs/="[B][COLOR="#FF0000"]00000000[/COLOR][/B]")then

I corrected it and now works perfectly. Thanks for your help, because you also noticed me other mistakes like the clock rising_edge and the reset.
 
Last edited:

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