[SOLVED] VHDL syntax for floating point

eengr · Mar 4, 2019

I am working on a VHDL code to generate PWM outputs

For now I would like to generate 50% duty cycle 50kHz waveforms

There are 6 PWM outputs

Each output needs to be 60 degrees out of phase with the previous one (Full cycle is 360 degrees)

So for 50MHz clock input signal, I am using counters for each individual waveform. The counters are incremented by 1 with each rising edge of clock
On time scale it should be something like:

So, when counter0 reaches (1000/2 = 500) then PWM(0) goes HIGH
When counter 1 reaches [(1000/6) + (1000/2)] = 666.666 = I used 666 in my code, PWM(1) goes HIGH

And so on...

I used the following VHDL code:

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity pwm is
    Port ( FPGA_OSC : in  STD_LOGIC;
           PWM_OUT : out  STD_LOGIC_VECTOR (5 downto 0));
end pwm;
 
architecture pwm_arch of pwm is
    signal pwm_sig : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
    signal counter0 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    signal counter1 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    signal counter2 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    signal counter3 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    signal counter4 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    signal counter5 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    
    signal brick1: STD_LOGIC_VECTOR (11 downto 0);
    signal brick2: STD_LOGIC_VECTOR (11 downto 0);
    signal brick3: STD_LOGIC_VECTOR (11 downto 0);
    signal brick4: STD_LOGIC_VECTOR (11 downto 0);
    signal brick5: STD_LOGIC_VECTOR (11 downto 0);
    signal brick6: STD_LOGIC_VECTOR (11 downto 0);  
    signal brick7: STD_LOGIC_VECTOR (11 downto 0);
    signal brick8: STD_LOGIC_VECTOR (11 downto 0);
    signal brick9: STD_LOGIC_VECTOR (11 downto 0);
    signal brick10: STD_LOGIC_VECTOR (11 downto 0);
    signal brick11: STD_LOGIC_VECTOR (11 downto 0);
    signal brick12: STD_LOGIC_VECTOR (11 downto 0);
    
    signal brick_s2: STD_LOGIC_VECTOR (11 downto 0);
    signal brick_s3: STD_LOGIC_VECTOR (11 downto 0);
    signal brick_s4: STD_LOGIC_VECTOR (11 downto 0);
    signal brick_s5: STD_LOGIC_VECTOR (11 downto 0);
    signal brick_s6: STD_LOGIC_VECTOR (11 downto 0);
--  constant brick3: STD_LOGIC_VECTOR (11 downto 0) := X"0502"; -- Input port 0 - 8 bits
    
    
begin
    brick1 <= X"1F4"; -- 500
    brick2 <= brick1 + brick1; -- 1000
    brick3 <= X"29A"; -- 666
    brick4 <= brick3 + brick1; -- 1166
    brick5 <= X"340"; -- 832
    brick6 <= brick5 + brick1;
    brick7 <= X"3E6"; --998
    brick8 <= brick7 + brick1;
    brick9 <= X"48C"; --1164
    brick10 <= brick9 + brick1;
    brick11 <= X"532"; -- 1330
    brick12 <= brick11 + brick1;
    
    
    brick_s2 <= brick3 - brick1;
    brick_s3 <= brick5 - brick1;
    brick_s4 <= brick7 - brick1;
    brick_s5 <= brick9 - brick1;
    brick_s6 <= brick11 - brick1;
    
    process (FPGA_OSC)
    begin
        if (rising_edge (FPGA_OSC)) then
            if (counter0 < brick1) then -- 500 is 1F4
                pwm_sig(0) <= '0';
                counter0 <= counter0 + 1;
            elsif (counter0 >= brick1 and counter0 < brick2) then -- 1000 is 3E8
                pwm_sig(0) <= '1';
                counter0 <= counter0 + 1;
            else
                counter0 <= (others => '0');
            end if;
        
        -- ***************************************************************
            if (counter1 < brick3) then -- 500 is 1F4
                pwm_sig(1) <= '0';
                counter1 <= counter1 + 1;
            elsif (counter1 >= brick3 and counter1 < brick4) then -- 1000 is 3E8
                pwm_sig(1) <= '1';
                counter1 <= counter1 + 1;
            else
                counter1 <= brick_s2;
            end if;
        -- ***************************************************************  
            if (counter2 < brick5) then -- 500 is 1F4
                pwm_sig(2) <= '0';
                counter2 <= counter2 + 1;
            elsif (counter2 >= brick5 and counter2 < brick6) then -- 1000 is 3E8
                pwm_sig(2) <= '1';
                counter2 <= counter2 + 1;
            else
                counter2 <= brick_s3;
            end if;
        -- ***************************************************************
            if (counter3 < brick7) then -- 500 is 1F4
                pwm_sig(3) <= '0';
                counter3 <= counter3 + 1;
            elsif (counter3 >= brick7 and counter3 < brick8) then -- 1000 is 3E8
                pwm_sig(3) <= '1';
                counter3 <= counter3 + 1;
            else
                counter3 <= brick_s4;
            end if;
        -- ***************************************************************
            if (counter4 < brick9) then -- 500 is 1F4
                pwm_sig(4) <= '0';
                counter4 <= counter4 + 1;
            elsif (counter4 >= brick9 and counter4 < brick10) then -- 1000 is 3E8
                pwm_sig(4) <= '1';
                counter4 <= counter4 + 1;
            else
                counter4 <= brick_s5;
            end if;
        -- ***************************************************************
            if (counter5 < brick11) then -- 500 is 1F4
                pwm_sig(5) <= '0';
                counter5 <= counter5 + 1;
            elsif (counter5 >= brick11 and counter5 < brick12) then -- 1000 is 3E8
                pwm_sig(5) <= '1';
                counter5 <= counter5 + 1;
            else
                counter5 <= brick_s6;
            end if;
        -- ***************************************************************
        
        
        end if;
        PWM_OUT(0) <= pwm_sig(0);
        PWM_OUT(1) <= pwm_sig(1);
        PWM_OUT(2) <= pwm_sig(2);
        PWM_OUT(3) <= pwm_sig(3);
        PWM_OUT(4) <= pwm_sig(4);
        PWM_OUT(5) <= pwm_sig(5);
        
    end process;
    
    
 
end pwm_arch;

I then used TestBench on ISIM to simulate the code and got the waveforms as below:

The problem I have is that: For the code that I am using I could only use whole number (integers) like 666 (0X29A) instead of 666.666 (or the answer of [(1000/6) + (1000/2)]

This consequently results in slightly different time difference between the waveforms from what they should have been

This could also be seen for the signals:

brick3, brick4, … , brick12 (in my VHDL code)

I am a beginner in VHDL and don’t know the best way to implement this. What is the recommended way / syntax to assign an answer of a function (like [(1000/6) + (1000/2)]) to a signal (say brick3)? Any help would be greatly appreciated

KlausST · Mar 4, 2019

Hi,

for a counter 0...1000 the expectable error is +/-0.05% (if you do the rounding correct).

Do you really care about this tiny error?

***
How I solve issues like this:
I use a counter TOP_value that is a multiple of 6. (minus 1)
--> 0..1001
then every 667 counts means exactly 60°

Klaus

FvM · Mar 4, 2019

The problem isn't specific for VHDL and has nothing to do with floating point arithmetic. A counter counts integer numbers, not float quantities.

Generating pulses with exact 60° phase shift and 50 % duty cycle is a simple integer math problem, you either need to change the pulse period a bit or use a different clock frequency. Another possible option is a fractional frequency divider with phase accumulator that can generate arbitrary frequencies, but with a jitter of 1 clock cycle.

Although obviously functional, this is a really ugly VHDL coding style. You may want to use recent ieee.unsigned library for your code, and a single decimal constant to set the pulse frequency.

eengr · Mar 4, 2019

KlausST said:
Hi,

for a counter 0...1000 the expectable error is +/-0.05% (if you do the rounding correct).

How did you calculate this?

Do you really care about this tiny error?

KlausST said:
***
How I solve issues like this:
I use a counter TOP_value that is a multiple of 6. (minus 1)
--> 0..1001
then every 667 counts means exactly 60°

Do you mean updating my code to something like this?

Code VHDL - [expand]
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brick1 <= X"1F4"; -- 500
    brick2 <= brick1 + brick1; -- 1000
    brick3 <= X"29B"; -- 667
    brick4 <= brick3 + brick1; -- 1167
    brick5 <= X"342"; -- 834
    brick6 <= brick5 + brick1; -- 1334
    brick7 <= X"3E9"; --1001
    brick8 <= brick7 + brick1; --1501
    brick9 <= X"490"; --1168
    brick10 <= brick9 + brick1; --1668
    brick11 <= X"537"; -- 1335
    brick12 <= brick11 + brick1; --1835

By changing the TOP_value of counter to 1001

Would I keep the 'brick1 = 500'? for 50% duty cycle?

FvM · Mar 4, 2019

The problem can be reduced to generate a 6*50 = 300 kHz clock tick. Either exact, needs a different input clock like 60 MHz, or approximate, e.g. 50e6 / 167 = 299.4 kHz. As said, simple integer math. Get your pocket calculator, try yourself.

eengr · Mar 4, 2019

FvM said:
The problem isn't specific for VHDL and has nothing to do with floating point arithmetic. A counter counts integer numbers, not float quantities.

Generating pulses with exact 60° phase shift and 50 % duty cycle is a simple integer math problem, you either need to change the pulse period a bit or use a different clock frequency. Another possible option is a fractional frequency divider with phase accumulator that can generate arbitrary frequencies, but with a jitter of 1 clock cycle.

Although obviously functional, this is a really ugly VHDL coding style. You may want to use recent ieee.unsigned library for your code, and a single decimal constant to set the pulse frequency.

Thanks for the feedback. Yes, I agree that there should be better coding style. As a first step I was trying to generate the wave forms (just in an open-loop method) that would resemble the final wave forms.

As a next step this code would need modification where Frequency & Duty cycle for each waveform could be modified. These two parameters will come from a micro-controller interfaced to FPGA over parallel port.

But even with this basic "ugly" implementation, what I am struggling with is to use the division operator.

Ok I agree that if I change the frequency slightly so that all my fraction answers come to an integer (as @Klauss suggested to change the top-level to 1002, & this will give me

Code VHDL - [expand]
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brick1 <= X"1F5"; -- 501
    brick2 <= brick1 + brick1; -- 1002
    brick3 <= X"29C"; -- 668
    brick4 <= brick3 + brick1; -- 1169
    brick5 <= X"343"; -- 835
    brick6 <= brick5 + brick1; -- 1336
    brick7 <= X"3EA"; --1002
    brick8 <= brick7 + brick1; --1503
    brick9 <= X"491"; --1169
    brick10 <= brick9 + brick1; --1670
    brick11 <= X"538"; -- 1336
    brick12 <= brick11 + brick1; --3171

In above expressions I could use:

Code VHDL - [expand]
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brick4 <= brick3 + brick1;

But if it try using say

Code VHDL - [expand]
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brick2 <= (1002/6) + (1002/2)

with intention of declaring 1000 as a fixed frequency constant somewhere in my code. I get error as I can't use '/' operator like this. So, my question is how to we implement division like this. If I were to declare 1000 or 1002 constant

FvM · Mar 4, 2019

No, you can't use the divide operator in this place. I'm not sure what you want achieve. If you want variable frequency or pulse width, it should be implemented differently.

KlausST · Mar 4, 2019

Hi,

How did you calculate this?

1 count out of 1000 = 0.1%

If you use rounding then the error becomes symmetric: +/-0.05%.

Klaus

ads-ee · Mar 4, 2019

They could just count to 667, 667, 666 and end up with an average that is exactly 666.666666, though with the 1 clock cycle jitter FvM mentioned earlier. Such a circuit is slightly simpler than the fractional freq divider and phase accum implementation, but isn't programmable.

vGoodtimes · Mar 5, 2019

The normal things to do are to increase the phase accumulator width and use serdes. eg, each cycle isn't an add by 1, but an add by 1.0001. Implemented as an accumulator that has 16+ extra fractional bits where the increment is 0x10001 or such. This has a 1 cycle jitter. This can be reduced by using the frequency synthesis with oserdes and the like to get the jitter down to 1/8th of a clock.

Bonus fact -- accumulators can be pipelined! Computing LSB's don't depend on MSB's at all. So you can run a 512 bit accumulator at the max clock of the FPGA if you want.

KlausST · Mar 5, 2019

Hi,

I also don't get your point why you want to divide.

To simplify things one tries to replace division by using integer multiplication.
In your case:
Instead of:

brick2 <= (1002/6) + (1002/2)

TOP = xf × 6 - 1 ( xf is the integer variable that defines the frequency)
brick2 = xf + xf × 3 = xf × 4

Mathematically I replaced
* your value "1002" with "167 × 6"... where "167" is the value of xf
* (1002 / 6) = 167 × 6 / 6 = 167 = xf
* (1002 / 2) = 167 × 6 / 2 = 167 × 3 = xf × 3

Klaus

eengr · Mar 6, 2019

Thanks for all the feedback.

Ok, I have the attached block diagram of proposed setup:

A micro-controller connected to FPGA over parallel port
8 data bits
8 address bits
1 Read bit
1 Write bit

The micro-controller will send all the 'up' and 'down' time of each waveform to FPGA & also frequency value.
During Run time these values could change (effectively changing the duty cycle of each waveform). The frequency for all of them would be same. If frequency is changed then it will change for all of them instead for one.

I started coding it from very basic level (as above) as I am not an expert VHDL programmer & slowly taking it step by step to first use constant values to generate the waveforms and then start introducing the variables.

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity pwm is
    Port ( FPGA_OSC : in  STD_LOGIC;
           PWM_OUT : out  STD_LOGIC_VECTOR (5 downto 0));
end pwm;
 
architecture pwm_arch of pwm is
    signal pwm_sig : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
 
--  signal counter0 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter1 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter2 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter3 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter4 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter5 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  
--  signal freq: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick1: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick2: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick3: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick4: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick5: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick6: STD_LOGIC_VECTOR (11 downto 0);  
--  signal brick7: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick8: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick9: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick10: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick11: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick12: STD_LOGIC_VECTOR (11 downto 0);
--  
--  signal brick_s1: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s2: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s3: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s4: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s5: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s6: STD_LOGIC_VECTOR (11 downto 0);
--  constant brick3: STD_LOGIC_VECTOR (11 downto 0) := X"0502"; -- Input port 0 - 8 bits
    
 
    
begin
 
 
    
    process (FPGA_OSC)
        variable counter0 : INTEGER range -9000 to 9000 :=0;--(11 downto 0) := (others => '0');
        variable counter1 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
        variable counter2 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
        variable counter3 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
        variable counter4 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
        variable counter5 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    
        variable freq: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick1: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick2: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick3: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick4: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick5: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick6: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);  
        variable brick7: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick8: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick9: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick10: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick11: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick12: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
    
        variable brick_s1: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s2: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s3: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s4: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s5: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s6: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
    
    
    
    begin
        freq := 1002; -- 1002
        brick1 := 501; -- 501
        brick2 := brick1 + brick1; -- 1002
        
            brick3 := 668; -- 668 (1*167 diff from 501)
            brick4 := 1169; -- 1169 (1*167 diff from 1002)
        brick5 := 835; -- 835 (2*167 diff from 501)
        brick6 := 935; -- 1336 (2*167 diff from 1002)
        brick7 := 1002; --1002 (3*167 diff from 501)
        brick8 := brick7 + brick1; --1503 (3*167 diff from 1002)
        brick9 := 1169; --1169 (4*167 diff from 501)
        brick10 := brick9 + brick1; --1670 (4*167 diff from 1002)
        brick11 := 1336; -- 1336 (5*167diff from 501)
        brick12 := brick11 + brick1; --3171 (5*167diff from 1002)
    
    
        brick_s1 := (brick1 + brick2) - (brick1 + freq); 
        brick_s2 := (brick3 + brick4) - (brick3 + freq); 
        brick_s3 := (brick5 + brick6) - (brick5 + freq); 
        brick_s4 := (brick7 + brick8) - (brick7 + freq); 
        brick_s5 := (brick9 + brick10) - (brick9 + freq); 
        brick_s6 := (brick11 + brick12) - (brick11 + freq); 
        if (rising_edge (FPGA_OSC)) then
            if (counter0 < brick1) then -- 500 is 1F4
                pwm_sig(0) <= '0';
                counter0 := counter0 + 1;
            elsif (counter0 >= brick1 and counter0 < brick2) then -- 1000 is 3E8
                pwm_sig(0) <= '1';
                counter0 := counter0 + 1;
            else
                counter0 := brick_s1;
            end if;
        
        -- ***************************************************************
            if (counter1 < brick3) then -- 500 is 1F4
                pwm_sig(1) <= '0';
                counter1 := counter1 + 1;
            elsif (counter1 >= brick3 and counter1 < brick4) then -- 1000 is 3E8
                pwm_sig(1) <= '1';
                counter1 := counter1 + 1;
            else
                counter1 := brick_s2;
            end if;
        -- ***************************************************************  
            if (counter2 < brick5) then -- 500 is 1F4
                pwm_sig(2) <= '0';
                counter2 := counter2 + 1;
            elsif (counter2 >= brick5 and counter2 < brick6) then -- 1000 is 3E8
                pwm_sig(2) <= '1';
                counter2 := counter2 + 1;
            else
                counter2 := brick_s3;
            end if;
        -- ***************************************************************
            if (counter3 < brick7) then -- 500 is 1F4
                pwm_sig(3) <= '0';
                counter3 := counter3 + 1;
            elsif (counter3 >= brick7 and counter3 < brick8) then -- 1000 is 3E8
                pwm_sig(3) <= '1';
                counter3 := counter3 + 1;
            else
                counter3 := brick_s4;
            end if;
        -- ***************************************************************
            if (counter4 < brick9) then -- 500 is 1F4
                pwm_sig(4) <= '0';
                counter4 := counter4 + 1;
            elsif (counter4 >= brick9 and counter4 < brick10) then -- 1000 is 3E8
                pwm_sig(4) <= '1';
                counter4 := counter4 + 1;
            else
                counter4 := brick_s5;
            end if;
        -- ***************************************************************
            if (counter5 < brick11) then -- 500 is 1F4
                pwm_sig(5) <= '0';
                counter5 := counter5 + 1;
            elsif (counter5 >= brick11 and counter5 < brick12) then -- 1000 is 3E8
                pwm_sig(5) <= '1';
                counter5 := counter5 + 1;
            else
                counter5 := brick_s6;
            end if;
        -- ***************************************************************
        
        
        end if;
        PWM_OUT(0) <= pwm_sig(0);
        PWM_OUT(1) <= pwm_sig(1);
        PWM_OUT(2) <= pwm_sig(2);
        PWM_OUT(3) <= pwm_sig(3);
        PWM_OUT(4) <= pwm_sig(4);
        PWM_OUT(5) <= pwm_sig(5);
        
    end process;
    
    
 
end pwm_arch;

The above code worked fine and I managed to simulate and generate waveforms of different duty cycles whilst keeping the frequency & phase difference constant

I would now like to replace all my constant values of 'bricks' with the values from a register (this register will be updated from micro controller - & the bus interface code is not added here) . As shown in my block diagram, I would have two 16-bit registers for each PWM as up1, dwn1,.....up2,dwn2,.....etc & one master frequency (time) register
So up1 will have time for PWM1 (going HIGH), dwn1 will have time for PWM1 (going LOW) and so on

As I have 'up' & 'dwn' time only which effectively define the ON time for a waveform, I would need to calculate the OFF time from the master frequency/time register

I am thinking of using the counter similar to how I used above in my code.

The counter start value

Code VHDL - [expand]
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brick_s1 := (brick1 + brick2) - (brick1 + freq); 
        brick_s2 := (brick3 + brick4) - (brick3 + freq); 
        brick_s3 := (brick5 + brick6) - (brick5 + freq); 
        brick_s4 := (brick7 + brick8) - (brick7 + freq); 
        brick_s5 := (brick9 + brick10) - (brick9 + freq); 
        brick_s6 := (brick11 + brick12) - (brick11 + freq);

could be negative (Please ignore the repetition of variables in above expressions that could be cancelled out (like in 1st line brick3 could be taken out from expression but I left it as it is for now). As they could be negative so I used them as integers (This is the 1st time I am using integers type in VHDL)

Now my registers like 'freq', 'up1', 'dwn1', etc would be of STD_LOGIC_VECTOR TYPE

and my counter is in integer type & then I would need to use the values from my register to calculate the start value of counter when the waveform goes LOW. I am struggling to do type conversion here.

I have tried the following:

Code VHDL - [expand]
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----------------------------------------------------------------------------------
 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity pwm is
    Port ( FPGA_OSC : in  STD_LOGIC;
           PWM_OUT : out  STD_LOGIC_VECTOR (5 downto 0));
end pwm;
 
architecture pwm_arch of pwm is
    signal pwm_sig : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
    signal up1: STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    signal dwn1: STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter0 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter1 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter2 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter3 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter4 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  signal counter5 : STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
--  
--  signal freq: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick1: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick2: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick3: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick4: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick5: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick6: STD_LOGIC_VECTOR (11 downto 0);  
--  signal brick7: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick8: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick9: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick10: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick11: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick12: STD_LOGIC_VECTOR (11 downto 0);
--  
--  signal brick_s1: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s2: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s3: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s4: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s5: STD_LOGIC_VECTOR (11 downto 0);
--  signal brick_s6: STD_LOGIC_VECTOR (11 downto 0);
--  constant brick3: STD_LOGIC_VECTOR (11 downto 0) := X"0502"; -- Input port 0 - 8 bits
    
 
    
begin
    up1 <= X"29C"; -- 668 decimal
    dwn1 <= X"491"; --1169 decimal
 
    
    process (FPGA_OSC)
        variable counter0 : INTEGER range -9000 to 9000 :=0;--(11 downto 0) := (others => '0');
        variable counter1 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
        variable counter2 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
        variable counter3 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
        variable counter4 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
        variable counter5 : INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    
        variable freq: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick1: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick2: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick3: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick4: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick5: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick6: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);  
        variable brick7: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick8: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick9: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick10: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick11: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick12: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
    
        variable brick_s1: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s2: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s3: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s4: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s5: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
        variable brick_s6: INTEGER range -9000 to 9000 :=0;--STD_LOGIC_VECTOR (11 downto 0);
    
    
    
    begin
        freq := 1002; -- 1002
        brick1 := 501; -- 501
        brick2 := brick1 + brick1; -- 1002
        brick3 := to_integer(up1);
        brick4 := to_integer(dwn1);
--  brick3 := 668; -- 668 (1*167 diff from 501)
--  brick4 := 1169; -- 1169 (1*167 diff from 1002)
        brick5 := 835; -- 835 (2*167 diff from 501)
        brick6 := 935; -- 1336 (2*167 diff from 1002)
        brick7 := 1002; --1002 (3*167 diff from 501)
        brick8 := brick7 + brick1; --1503 (3*167 diff from 1002)
        brick9 := 1169; --1169 (4*167 diff from 501)
        brick10 := brick9 + brick1; --1670 (4*167 diff from 1002)
        brick11 := 1336; -- 1336 (5*167diff from 501)
        brick12 := brick11 + brick1; --3171 (5*167diff from 1002)
    
    
        brick_s1 := (brick1 + brick2) - (brick1 + freq); 
        brick_s2 := (brick3 + brick4) - (brick3 + freq); 
        brick_s3 := (brick5 + brick6) - (brick5 + freq); 
        brick_s4 := (brick7 + brick8) - (brick7 + freq); 
        brick_s5 := (brick9 + brick10) - (brick9 + freq); 
        brick_s6 := (brick11 + brick12) - (brick11 + freq); 
        if (rising_edge (FPGA_OSC)) then
            if (counter0 < brick1) then -- 500 is 1F4
                pwm_sig(0) <= '0';
                counter0 := counter0 + 1;
            elsif (counter0 >= brick1 and counter0 < brick2) then -- 1000 is 3E8
                pwm_sig(0) <= '1';
                counter0 := counter0 + 1;
            else
                counter0 := brick_s1;
            end if;
        
        -- ***************************************************************
            if (counter1 < brick3) then -- 500 is 1F4
                pwm_sig(1) <= '0';
                counter1 := counter1 + 1;
            elsif (counter1 >= brick3 and counter1 < brick4) then -- 1000 is 3E8
                pwm_sig(1) <= '1';
                counter1 := counter1 + 1;
            else
                counter1 := brick_s2;
            end if;
        -- ***************************************************************  
            if (counter2 < brick5) then -- 500 is 1F4
                pwm_sig(2) <= '0';
                counter2 := counter2 + 1;
            elsif (counter2 >= brick5 and counter2 < brick6) then -- 1000 is 3E8
                pwm_sig(2) <= '1';
                counter2 := counter2 + 1;
            else
                counter2 := brick_s3;
            end if;
        -- ***************************************************************
            if (counter3 < brick7) then -- 500 is 1F4
                pwm_sig(3) <= '0';
                counter3 := counter3 + 1;
            elsif (counter3 >= brick7 and counter3 < brick8) then -- 1000 is 3E8
                pwm_sig(3) <= '1';
                counter3 := counter3 + 1;
            else
                counter3 := brick_s4;
            end if;
        -- ***************************************************************
            if (counter4 < brick9) then -- 500 is 1F4
                pwm_sig(4) <= '0';
                counter4 := counter4 + 1;
            elsif (counter4 >= brick9 and counter4 < brick10) then -- 1000 is 3E8
                pwm_sig(4) <= '1';
                counter4 := counter4 + 1;
            else
                counter4 := brick_s5;
            end if;
        -- ***************************************************************
            if (counter5 < brick11) then -- 500 is 1F4
                pwm_sig(5) <= '0';
                counter5 := counter5 + 1;
            elsif (counter5 >= brick11 and counter5 < brick12) then -- 1000 is 3E8
                pwm_sig(5) <= '1';
                counter5 := counter5 + 1;
            else
                counter5 := brick_s6;
            end if;
        -- ***************************************************************
        
        
        end if;
        PWM_OUT(0) <= pwm_sig(0);
        PWM_OUT(1) <= pwm_sig(1);
        PWM_OUT(2) <= pwm_sig(2);
        PWM_OUT(3) <= pwm_sig(3);
        PWM_OUT(4) <= pwm_sig(4);
        PWM_OUT(5) <= pwm_sig(5);
        
    end process;
    
    
 
end pwm_arch;

But it gives me errors.

What I did was:

Code VHDL - [expand]
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architecture pwm_arch of pwm is
    signal pwm_sig : STD_LOGIC_VECTOR (5 downto 0) := (others => '0');
    signal up1: STD_LOGIC_VECTOR (11 downto 0) := (others => '0');
    signal dwn1: STD_LOGIC_VECTOR (11 downto 0) := (others => '0');

Declared two 12 bits signal vectors up1 & dwn1

Code VHDL - [expand]
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begin
    up1 <= X"29C"; -- 668 decimal
    dwn1 <= X"491"; --1169 decimal

Assigned some fixed values to above signals

Code VHDL - [expand]
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begin
        freq := 1002; -- 1002
        brick1 := 501; -- 501
        brick2 := brick1 + brick1; -- 1002
        brick3 := to_integer(up1);
        brick4 := to_integer(dwn1);

Tried loading the values from up1 & dwn1 to brick3 & brick4

& when I try synthesizing, I get the error as:

Code VHDL - [expand]
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ERROR:HDLCompiler:432 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 115: Formal <arg> has no actual or default value.
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/numeric_std.vhd" Line 701. arg is declared here
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/numeric_std.vhd" Line 701. arg is declared here
ERROR:HDLCompiler:541 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 115: Type integer is not an array type and cannot be indexed.
ERROR:HDLCompiler:432 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 116: Formal <arg> has no actual or default value.
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/numeric_std.vhd" Line 701. arg is declared here
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/numeric_std.vhd" Line 701. arg is declared here
ERROR:HDLCompiler:541 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 116: Type integer is not an array type and cannot be indexed.
ERROR:HDLCompiler:854 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 40: Unit <pwm_arch> ignored due to previous errors.

Any help here would be greatly appreciated.

ads-ee · Mar 6, 2019

I noticed you switched from using signals for most everything to using exclusively all variables...
You might want to take a look at this post I made about what happens when you use variables in your code, especially when you use them for counters...
https://www.edaboard.com/showthread.php?376686-Im-doing-a-7-segment-multiplexing-code-but-I-have-an-error-and-the-bcd-part-is-wrong&p=1613708&viewfull=1#post1613708
In that post I show synthesis results of using variables for counters and using signals for counters.

eengr · Mar 11, 2019

ads-ee said:
I noticed you switched from using signals for most everything to using exclusively all variables...
You might want to take a look at this post I made about what happens when you use variables in your code, especially when you use them for counters...
https://www.edaboard.com/showthread.php?376686-Im-doing-a-7-segment-multiplexing-code-but-I-have-an-error-and-the-bcd-part-is-wrong&p=1613708&viewfull=1#post1613708
In that post I show synthesis results of using variables for counters and using signals for counters.

OK thanks for the feedback. I had a look at your comparison report which concludes that variables use more resources than signals and also contribute to additional delays. Very useful information (thanks for sharing it)

My question is:
My counter 'start' value for OFF-TIME could be a 'NEGATIVE' number like:

Code VHDL - [expand]
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brick_s1 := (brick1 + brick2) - (brick1 + freq); 
        brick_s2 := (brick3 + brick4) - (brick3 + freq); 
        brick_s3 := (brick5 + brick6) - (brick5 + freq); 
        brick_s4 := (brick7 + brick8) - (brick7 + freq); 
        brick_s5 := (brick9 + brick10) - (brick9 + freq); 
        brick_s6 := (brick11 + brick12) - (brick11 + freq);

& I don't think I could use signals for negative numbers OR can I?

Secondly, I must be doing something wrong in type casting as mentioned in my last post:

Code VHDL - [expand]
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begin
        freq := 1002; -- 1002
        brick1 := 501; -- 501
        brick2 := brick1 + brick1; -- 1002
        brick3 := to_integer(up1);
        brick4 := to_integer(dwn1);

But I don't know what exactly I am doing wrong here. It would be greatly appreciated if you could help me in correcting my syntax here please

TrickyDicky · Mar 11, 2019

Its a mistake to have the blanket idea that variables use more resource than signals.
Variables can use exactly the same resouce - but they are more affected by how they are used.
Because they can be much more affected by context, it is much safer to use signals until you know what the real difference is.

If you want negative numbers, then used the signed type. You could also use integer but you need to be more careful about ranges.
Again, with full understanding of the consequences, integers should create the same logic as the signed type.

Your errors occur because there is no function called "to_integer" that acts on a std_logic_Vector. You need to convert to signed/unsigned first then to_integer

Code:

brick3 := to_integer( signed(up1) );

There are plenty of tutorials for numeric_std out there.

eengr · Mar 11, 2019

TrickyDicky said:
Its a mistake to have the blanket idea that variables use more resource than signals.
Variables can use exactly the same resouce - but they are more affected by how they are used.
Because they can be much more affected by context, it is much safer to use signals until you know what the real difference is.

If you want negative numbers, then used the signed type. You could also use integer but you need to be more careful about ranges.
Again, with full understanding of the consequences, integers should create the same logic as the signed type.

Your errors occur because there is no function called "to_integer" that acts on a std_logic_Vector. You need to convert to signed/unsigned first then to_integer

Code:

brick3 := to_integer( signed(up1) );

There are plenty of tutorials for numeric_std out there.

Thanks for the feedback.

I have tried the following syntax: (All other code remains the same, I could share the code again if that would be helpful)

Code VHDL - [expand]
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begin
    freq := 1002; -- 1002
    brick1 := 501; -- 501
    brick2 := brick1 + brick1; -- 1002
    brick3 := to_integer( unsigned (up1) );
    brick4 := to_integer( unsigned (dwn1) );

But I still get errors when I try to synthesize:

Code VHDL - [expand]
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Parsing entity <pwm>.
Parsing architecture <pwm_arch> of entity <pwm>.
ERROR:HDLCompiler:607 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 115: Multiple declarations of unsigned included via multiple use clauses; none are made directly visible
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/syn_arit.vhd" Line 27. unsigned is declared here
Another match is here
ERROR:HDLCompiler:432 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 115: Formal <arg> has no actual or default value.
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/numeric_std.vhd" Line 701. arg is declared here
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/numeric_std.vhd" Line 701. arg is declared here
ERROR:HDLCompiler:541 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 115: Type integer is not an array type and cannot be indexed.
ERROR:HDLCompiler:607 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 116: Multiple declarations of unsigned included via multiple use clauses; none are made directly visible
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/syn_arit.vhd" Line 27. unsigned is declared here
Another match is here
ERROR:HDLCompiler:432 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 116: Formal <arg> has no actual or default value.
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/numeric_std.vhd" Line 701. arg is declared here
INFO:HDLCompiler:1408 - "/build/legacysi10/P.20160913/rtf/vhdl/xst/src/numeric_std.vhd" Line 701. arg is declared here
ERROR:HDLCompiler:541 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 116: Type integer is not an array type and cannot be indexed.
ERROR:HDLCompiler:854 - "/home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd" Line 40: Unit <pwm_arch> ignored due to previous errors.
VHDL file /home/ise/Shared_Folder/Fpga_Vhd/FCBR_Supply/FCBR_Test/PWM.vhd ignored due to errors
--> 
 
 
Total memory usage is 311324 kilobytes
 
Number of errors   :    7 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
 
 
Process "Synthesize - XST" failed

TrickyDicky · Mar 11, 2019

delete use ieee.std_logic_arith.all; from your code. Its causing a conflict (and its non-standard)

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