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Why are the most critical signals in Digital Circuitry are Active low ?

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kaushikrvs

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The most critical signals like reset signals for flip flops and the control signal of various communication interfaces (CS/SS for the SPI) are often active low. What advantages do they bring over having an active high signal ?
 

No supply equals with low level. If there is a system failure caused supply drop-out that will generate automatic reset for example.
 

I have also seen many cases of active-high reset. Totally depends on the system architect.
 

The most critical signals like reset signals for flip flops and the control signal of various communication interfaces (CS/SS for the SPI) are often active low. What advantages do they bring over having an active high signal ?
Hello
As you said most critical signals (but not all) are active low. It all depends on one's application for real. But generally active low is chosen as when you are having control signals interfaced with micro-controllers,and most controllers have I/O pins high on default. So I guess that could be one of the reasons why.. Other reasons includes usually system application requirements..
 

I was told (about 30 years ago) that it is harder for noise to make a low look high compared to noise making a high look low, so critical signals were made low. I think it goes back to the difference between input high current and input low current.
 

If a signal is pulled low it will always remain low and be seen as a low before, during and after powerup.

Whereas power sequencing issues can make it hard to guarantee the same for a high.
 

Hi,

I´m really interested in the answer.

If a signal is pulled low it will always remain low and be seen as a low before, during and after powerup.

Whereas power sequencing issues can make it hard to guarantee the same for a high.

But for many circuits it really may cause problems when a signal is considered LOW at statup.
I think about
* the *RD and *WR signals coming out of a processor. I don´t think it´s a good idea to have both *RD and *WR active at power up.
* or the *CS signals of SPI slaves. When they are LOW, then they enable the driver for MISO ... causing short circuit currents...
* or similar the *OE signal of parallel SRAM, EEPROM, FLASH .. chips

I think for these signal it´s more safe to use HIGH active logic.

TTL legacy and/or noise issues sound reasonable.

Klaus
 

I was told (about 30 years ago) that it is harder for noise to make a low look high compared to noise making a high look low, so critical signals were made low. I think it goes back to the difference between input high current and input low current.

It's back to the TTL days like FvM said, with the old TTL input levels and output levels

Input voltage ranges
Vih = 2V
Vil = 0.8V

output voltage ranges
Voh = 2.7V
Vol = 0.5V

Voh - Vih = 0.7V (noise margin)
Vil - Vol = 0.3V (noise margin)

For a signal that goes active low, there is more noise margin when the signal is high to continue to be interpreted as a high, hence important signals like resets were always active low, because if they were high coupled noise on the signal were far less likely to cause the signal to drop below the Vih level, generating unintended resets.

CMOS has balanced noise margins and rail to rail output switching and therefore using either active high or active low makes no difference.
 

An observation, and it is only an observation: I also see many open collector ICs (The LM339 is a perfect example) which use a NPN transistor as the output device. An active signal from such a device will be low.
Back in the day when those devices were designed, an integrated NPN transistor was faster than an integrated vertical PNP.
Again, it is only an observation.

But I believe, like others have stated, the real reason is the TTL input architecture. A floating TTL input will be a logic high (although with less than ideal noise immunity). For a logic low one has to purposefully drive the signal towards ground.
 

Hi,

Input voltage ranges
Vih = 2V
Vil = 0.8V

output voltage ranges
Voh = 2.7V
Vol = 0.5V

I can only partly agree.
Wikipedia as well as Texas Instruments SN7404 datasheet (randomly chosen) says:
Input voltage ranges
Vih = 2V
Vil = 0.8V

output voltage ranges
Voh = 2.4V
Vol = 0.4V

Which leads to a symmetrical noise margin of 0.4V.

***

But the drive strength is very different (TI SN7404):
I_OH = -0.4mA
I_OL = 16mA
--> a ratio of 40!

Maybe this made TTL LOW signals more immune against noise than HIGH signals.


Klaus
 

To the best of my knowledge, this is only due to legacy reasons. If we are talking about noise in a digital signal due to coupling, going 1->0 or 0->1 is equally difficult (easy).
 

TTL had a natural pullup so an open signal would
go to the inactive state if active=L.

Open-collector gate options permitted wire-AND /
party-line connections, for example if you had
multiple reset actors and a single reset pin and
were too cheap to buy another 74LSwhatever to
perform the logic.

In CMOS with mixed supply rails, ground is about
the only thing people can agree on; an active low
input with a local pullup can be driven by an open
drain / open collector output from any supply domain
(if the ground is indeed pervasive / common).
 

Hi,

I´m really interested in the answer.



But for many circuits it really may cause problems when a signal is considered LOW at statup.
I think about
* the *RD and *WR signals coming out of a processor. I don´t think it´s a good idea to have both *RD and *WR active at power up.
* or the *CS signals of SPI slaves. When they are LOW, then they enable the driver for MISO ... causing short circuit currents...
* or similar the *OE signal of parallel SRAM, EEPROM, FLASH .. chips
Klaus

I'm just saying if you want to guarantee a signal is in a certain state, and seen by everybody to be in that state during power-up, particularly in a multi-rail system, low is the safest bet.

I agree I don't think that's an answer for why all the listed signals are active low (SPI chip select for example) but it's something on my mind when choosing polarity (when I can).

On a recent design I had a signal crossing isolation and going to an active low driver that I did not want glitching on during power-up. We could have added pull-ups at every leg but I eventually decided it was impossible to ensure 'no one' saw it as low ever during power up and added an additional active high enable.


I also wonder whether the question is actually correct: Are more 'critical' signals actually active low? Seems hard to define or quantify.
 

Hi,

and added an additional active high enable.
This is how I do, too.

I also wonder whether the question is actually correct: Are more 'critical' signals actually active low? Seems hard to define or quantify.
I agree.

Klaus
 

the control signal of various communication interfaces (...) are often active low

Regardless of aspects related to EMI weakness dealing with external signals, a side advantage on being an input inactive high - and having proper pull-up biasing - is that you can straightly couple an open collector output with no extra devices needed, no (weak) power added to the bus, as can be seen with the 8051 I/Os for example.
 

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