Cesar0182
Member level 5
Greetings ... tell you that a couple of days ago I am trying to translate a project from verilog to vhdl using Vivado 2017.3, and one of the modules I am translating refers to two templates that I can not find in the project (ODDR, OSERDESE2). that's why I can not synthesize my project since I have the following error that is shown in the attached image.
Can someone tell me how I can add these templates to my vhdl project, thanks in advance. I leave attached the vhdl file of g1_hotlink_pim.v and g1_hotlink_pim_vhdl.vhd where I have the problem.
Can someone tell me how I can add these templates to my vhdl project, thanks in advance. I leave attached the vhdl file of g1_hotlink_pim.v and g1_hotlink_pim_vhdl.vhd where I have the problem.