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[SOLVED] Add templates ODDR and OSERDESE2 in vhdl project

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Cesar0182

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Greetings ... tell you that a couple of days ago I am trying to translate a project from verilog to vhdl using Vivado 2017.3, and one of the modules I am translating refers to two templates that I can not find in the project (ODDR, OSERDESE2). that's why I can not synthesize my project since I have the following error that is shown in the attached image.

oddr_oserdese2_error.PNG

Can someone tell me how I can add these templates to my vhdl project, thanks in advance. I leave attached the vhdl file of g1_hotlink_pim.v and g1_hotlink_pim_vhdl.vhd where I have the problem.
 

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  • g1_hotlink_pim_vhdl.rar
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The problem is writing VHDL without understanding the language rules.

You need a component declaration or library use statement for the Xilinx low level primitives.

Read the Xilinx library guide for your FPGA family and follow the instructions, e.g. insert

Code VHDL - [expand]
1
2

Library UNISIM; 
use UNISIM.vcomponents.all;
 

Thanks FvM, with your help I have managed to solve my problem
 

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