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latches in timing (do latches get timed as destination or as combo logic)

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stanford

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If the tool sees a latch in the timing path, does it try to meet setup/hold time to the latch or does it assume it is transparent and find the destination flop?

It needs to meet both timing requirements as destination and as combo logic right? How does this work?
 

stanford said:
If the tool sees a latch in the timing path, does it try to meet setup/hold time to the latch or does it assume it is transparent and find the destination flop?

It needs to meet both timing requirements as destination and as combo logic right? How does this work?
Click to expand...

It has to meet both, and for this reason the tools really dislike latch-based designs. The problem gets out of hand when you have multiple latches back to back, you have to consider all combinations of transparent/latching combinations. In general, we try not to use latches unless there is a real need to optimize a certain path to the max, almost by hand.
 
stanford said:
If the tool sees a latch in the timing path, does it try to meet setup/hold time to the latch or does it assume it is transparent and find the destination flop?

It needs to meet both timing requirements as destination and as combo logic right? How does this work?
Click to expand...

Synthesis tool should look at both paths as previously stated. There are few processor based companies that uses latch based designs with internal timing tools to gain from timing borrowing and stealing. However, you should always use negative level latch followed by positive level latch. In other words, no 3 latches should be transparent at the same time.
 

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