Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to debug pattern mismatch during simulation of SOC level patterns- DFT

Status
Not open for further replies.
F

finsiherfish

Newbie level 4
Joined
Feb 26, 2019
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
28
Hello All,

I am a beginner in DFT field so can anyone elaborate in detail steps to how to debug a pattern mismatch during ATPG simulation at SOC level - ( I know a couple of types of simulations Readback and TorteSim) and please let me know any common mismatches you see regularly.


Thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top