Choosing backplane bus transceiver

Our team has developed a several controller boards for our current Projects for over three years. With little modifications we have used this board in several projects so far. Its structure is as follows:



As you see almost all peripherals are connected to FPGA and The data bus between FPGA and CPU is a parallel bus (16 data line,12 addr line)based on FSMC-FPGA is like an SRAM for MCU-

Now we have decided to upgrade it to a modular system, here is system sketch:



At the moment we are investigating about buses and Backplanes and trying to choose one.

here are some of our requirement:

• we need one/two CPU slots(s)and modular peripherals on a multipoint Bus.
• all nodes can send/recv data to/from the CPU slot(s)
• CPU shall assess other slots like memory blocks (FPGAs on the slots act as memory for the CPU slot).
• the communication speed of between CPU and peripherals Must be at least 25Mbit/s.
• it would be better to have hot-swap capability but it is not essential now
• we do not need communications between peripheral slots

questions:

1. what are possible or recommended choices for "Bus Drivers and Receivers" for our system? as far as i know here are some:
   • Backplane Transceiver Logic (BTL) e.g. SN74FB1651
   • General-Purpose Interface Logic e.g. 74ALVT162245DL
   • Gunning Transceiver Logic Plus (GTLP) e.g. SN74GTLPH32912
   • VME64 e.g. SN74VMEH22501A
2. what are possible or recommended choices for "Data Link (node-to-node validity and integrity of the transmission)" for system? as far as i know here are some:
   1. PCI/CompactPCI
3. Is there any application note,sample or reference design for a parallel communication (add/data bus) over backplane on a uC?
4. Is there a Bus controller to Transceive our current parallel data over backplane on each slots so that we don't care about the bus or packplane

Hi,

honestly, i´d use differential signals.

RS422/RS485, or more "up to date" LVDS.

Also read about SERDES via LVDS.
--> there are ready to by interface chips and FPGAs with built in interface hardware.

Klaus

honestly, i´d use differential signals.

RS422/RS485, or more "up to date" LVDS.

Click to expand...

It's a multidrop bus, so at least BLVDS.

Hi,

You are right.

I just want to point out the "differential" signaling.

If the "mutlidrop" is a must, then I assume SERDES won´t work, because it needs some time to sync on the incoming datatream.

Klaus

thanks for the answers,
so you both recommend to use differential signalling:???:
here is my sketch, i am going to use SN65LVDM1676 any suggestions ?

I think i should use 96 pin DIN connectors for the back-plane. any suggestions for the designing back-plane ping mappings?

Hi,

a design starts with requirements.
Thus it´s important to know about the bus timing. You never mentioned it before. Thus all our answers is just guessing...
--> Decide the requirements - at least for yourself - first.

*****

I think i should use 96 pin DIN connectors for the back-plane. any suggestions for the designing back-plane ping mappings?

Click to expand...

At both ends of the backplane you need to install termination resistors.
Choose the pin mapping in a way that the pairs are next to each other and the wiring on the backplane is simple and keeps the differential characteristic impedance close to ideal.

Do an internet search for
* differential microstrip
* differential stripline
* broadside coupled stripline

Klaus

thanks KlausST

KlausST said:

Thus it´s important to know about the bus timing. You never mentioned it before. Thus all our answers is just guessing...

Click to expand...

as i mentioned in first post, the communication speed between CPU (slot) and peripherals(cards) Must be at least 25Mbit/s.
It is not a high bit-rate, what i need here is low bit error rate in bus.

Hi,

25Mbit/s...maybe is a good information for an async serial interface, but not for yor application.

You most probalbly have some control signals..and I expect a lot of detailed specifications between address and data, control signals and data. Your periferals will have specified timing, too. Now the backplane will add some delay, too.

You don't need to send us all the values, but I strongly recommend you to check the timing.

Klaus