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[moved] Lattice CPLD Reconstruction and porting

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wwfeldman

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I have a Lattice CPLD device (ispLSI1016) whose program was done about early 1990s. I want to rebuild the source so it can be ported to a new device. I have some time, as we have some stock, but I want it done before stock runs out. I have the output files, but not the input file.

It was programmed with Lattice pDS Version 5.0. I would like to borrow a hard copy of the documentation, to be sure I understand the language conventions and notation. Alternatively, I would like to know where the documentation is available online. I do not need or want the software.
 

Re: Lattice CPLD Reconstruction and porting

There is no way (at least that I know of) that you are going to be able to recreate source code from a bit file. Do you even know if the source was VHDL, Verilog, or whatever? You MIGHT be able to create some some gate-level schematic, but, personally, I would just quit and find a different job.
 

Re: Lattice CPLD Reconstruction and porting

Given there was another thread from 2 1/2 years ago looking for pDS and never managed to find it. I'd say you are unlikely to ever obtain it or it's documentation. There is also not going to be any part of the documentation that explains how to take a programming file and convert it back to source code.

You might have a better shot of putting a logic analyzer on the pins of the CPLD and run the part through it's paces and reverse engineer what it does instead of trying to extract the design out of a logic array programming file. Admittedly if you are glutton for punishment, you have more of a chance of extracting the design from a logic array of a CPLD (than say even a small FPGA) given the CPLD at least has a somewhat regular structure that directly maps to the programmable logic arrays.
 

Re: Lattice CPLD Reconstruction and porting

my mistake.
I have a bunch of files: .FXP, .JED, .LBK, .ldf, .LIF, .LPR, ,RP1, .STA.
I never intended to try to reconstruct from the JEDEC file.

The .ldf file is text and looks like ABEl, Verilog or VHDL equations, or an early version thereof.

The and, ors, clocks and enables have been straightforward.
There is some notation that I have not been able to get a definite handle on.
Therefore I was looking for the documentation.

As I recall that thread from 2 years ago was looking for software.
Since you never know what someone still has on a shelf, I asked for documentation.
 

Re: Lattice CPLD Reconstruction and porting

Can't you post some of these equations with the notation that you can't interpret? Some us may know what they are. I haven't used ABEL for decades, but I or someone else may remember if we see the code.

- - - Updated - - -

BTW, I'm moving your thread to the programmable logic section as it's not so much about software links, but is about a porting from ABEL or something similar to a modern CPLD/FPGA.

- - - Updated - - -

Have you looked over this document? **broken link removed**
 

Xilinx's ISE webpack or some other stand-alone tool has a tool for converting ABEL to VHDL (and probably Verilog). It just happens that I used it for a Lattice CPLD as well. It flagged hardware specific things that weren't generic (in my case I think they used dedicated shift registers, it's been a few years) but reading the Lattice datasheet I was able to re-create those sections. Check http://www.xilinx.com/support/answers/17000.html.
 

per ads-ee's suggestion, i have copied the .ldf file:
it took a little while to write out the questions

the .ldf file is in uppercase
questions and comments are in lowercase

the cpld is the timing functionality of a watchdog for three relays, RL1, RL2 and RL3
B4, B5, B6, B7 are 4 bits from a microprocessor that activates watchdog functions

question - what do these options do?
OPTION ISP ON;
OPTION PULLUP ON;

question: I assume the (following) macro CGUS14 (counter, grey(?), up, style1(?), 4 bit ) is called out,
with the Q's, clk, enable, and clear I/O specified and the equations added by the software.

the MACROCOMMENT calls out enable, sync preset and async clear, but i only see enable and async clear
i don't see any input for sync preset, nor a control for sync preset
I am inclined to assume the comment is incorrect and the sync preset should be removed

unless I made a mistake analyzing the equations, I don't see this behaving as a grey counter.

Code: 
DECLARE
  MACRO CGUS14 (Q0,Q1,Q2,Q3,CLK,EN,CD);
      MACROTYPE  RX;
      MACROGROUP gccntr;
      MACROCOMMENT 4-bit up counter      enable, Sync preset and Async clear;
      SIGTYPE [Q0,Q1,Q2,Q3] REG OUT;
      EQUATIONS
         [Q0,Q1,Q2,Q3].CLK = CLK;
         [Q0,Q1,Q2,Q3].RE = CD;
         Q0 = (Q0 & !EN) # (!Q3 & !Q2 & !Q1 & EN) #
              (!Q3 & Q2 & Q1 & EN) # (Q3 & Q2 & !Q1 & EN) #
              (Q3 & !Q2 & Q1 & EN);
         Q1 = (Q1 & !EN) # (Q1 & !Q0 & EN) #
              (!Q3 & !Q2 & Q0 & EN) # (Q3 & Q2 & Q0 & EN);
         Q2 = (Q2 & !EN) # (!Q3 & Q1 & !Q0 & EN) #
              (Q2 & !Q1 & EN) # (Q2 & Q0 & EN);
         Q3 = (Q3 & !EN) # (Q2 & !Q1 & !Q0 & EN) #
              (Q3 & Q0 & EN) # (Q3 & Q1 & EN);
      END;
   END;

this macro seems fairly straightforward, with no issues
except for inconsistency with comments compared to the previous macro.
counter, binary, up (style 58_1 ??)

Code: 
  MACRO CBU58_1 ([Q0..Q3],EN,CLK,CD);
      MACROTYPE  RX;
      MACROGROUP bincntr;
      MACROCOMMENT First submacro of 8-bit up counter with Async clear;
      SIGTYPE [Q0..Q3] REG OUT;
      EQUATIONS
         [Q0..Q3].CLK = CLK;
         [Q0..Q3].RE = CD;
         Q0 = Q0 $$ EN;
         Q1 = (Q0.Q & EN) $$ Q1;
         Q2 = (Q0.Q & Q1.Q & EN) $$ Q2;
         Q3 = (Q0.Q & Q1.Q & Q2.Q & EN) $$ Q3;
      END;
   END;

  MACRO CBU58_2 ([Q4..Q7],[Q0..Q3],EN,CLK,CD);
      MACROTYPE  RX;
      MACROGROUP bincntr;
      MACROCOMMENT Second submacro of 8-bit up counter with Async clear;
      SIGTYPE [Q4..Q7] REG OUT;
      EQUATIONS
         [Q4..Q7].CLK = CLK;
         [Q4..Q7].RE = CD;
         Q4 = (Q0 & Q1 & Q2 & Q3 & EN) $$ Q4;
         Q5 = (Q0 & Q1 & Q2 & Q3 & Q4 & EN) $$ Q5;
         Q6 = (Q0 & Q1 & Q2 & Q3 & Q4 & Q5 & EN) $$ Q6;
         Q7 = (Q0 & Q1 & Q2 & Q3 & Q4 & Q5 & Q6 & EN) $$ Q7;
      END;
   END;

  MACRO CBU54 ([Q0..Q3],EN,CLK,CD);
      MACROTYPE  RX;
      MACROGROUP bincntr;
      MACROCOMMENT First submacro of 8-bit up counter with Async clear;
      SIGTYPE [Q0..Q3] REG OUT;
      EQUATIONS
         [Q0..Q3].CLK = CLK;
         [Q0..Q3].RE = CD;
         Q0 = Q0 $$ EN;
         Q1 = (Q0.Q & EN) $$ Q1;
         Q2 = (Q0.Q & Q1.Q & EN) $$ Q2;
         Q3 = (Q0.Q & Q1.Q & Q2.Q & EN) $$ Q3;
      END;
   END;
END;  //DECLARE

global logic block assignments
not clear if this is assigned by user or by software

Code: 
SYM GLB  B7  1  RL3_A;
 CBU58_1 ([RL3Q0..RL3Q3],RL3EN,CLK8,!RL3EN);
END;

SYM GLB  B6  1  RL3_B;
 CBU58_2 ([RL3Q4..RL3Q7],[RL3Q0..RL3Q3],RL3EN,CLK8,!RL3EN);
END;

SYM GLB  A0  1  RL1_A;
 CBU58_1 ([RL1Q0..RL1Q3],RL1EN,CLK8,!RL1EN);
END;

SYM GLB  A1  1  RL1_B;
 CBU58_2 ([RL1Q4..RL1Q7],[RL1Q0..RL1Q3],RL1EN,CLK8,!RL1EN);
END;

in following section:
question: RL1 is assigned to pin 28 and is an output (in pin I/O assignment section below)
I am not sure what all of the extensions and variations mean:

output macrocell seems to be a clocked D latch with enable

Code: 
RL1                  output pin 
RL1EN              enable
RL1.PIN            feedback from output pin
!RL1_TO.PIN    negated intermediate signal below
RL1EN.D          D input to another macrocell for enable??
RL1_TO            intermediate signal based on external setting (RL1_4,  _8 and _16) and counter output (Q5, Q6, Q7)
RL1EN.CLK      clock for D latch

question: I am inclined to accept the TO extension as a Time Out, since the circuit is a watchdog, so what is the difference between RL1_TO and !RL1_TO.PIN (other than the negation)

question: RL1EN.D depends on RL1EN but I do not find RL1EN defined anywhere


Code: 
SYM GLB  A4  1  RL1_CONTROL;
EQUATIONS
RL1	=	RL1EN
	#	RL1.PIN & !RL1_TO.PIN;

RL1EN.D =	(!_B5 # WD_TO)
	#	RL1EN & !RL1_TO.PIN;

RL1_TO	=	!_RL1_4 & RL1Q5
	#	!_RL1_8 & RL1Q6
	#	!_RL1_16 & RL1Q7;

RL1EN.CLK	=	CLK8;
END;
END;

SYM GLB  A5  1  RL2_CONTROL;
EQUATIONS
RL2	=	RL2EN
	#	RL2.PIN & !RL2_TO.PIN;

RL2EN.D =	(!_B6 # WD_TO)
	#	RL2EN & !RL2_TO.PIN;

RL2_TO	=	!_RL2_4 & RL2Q5
	#	!_RL2_8 & RL2Q6
	#	!_RL2_16 & RL2Q7;

RL2EN.CLK	=	CLK8;

END;
END;

SYM GLB  A2  1  RL2_A;
 CBU58_1 ([RL2Q0..RL2Q3],RL2EN,CLK8,!RL2EN);
END;

SYM GLB  A3  1  RL2_B;
 CBU58_2 ([RL2Q4..RL2Q7],[RL2Q0..RL2Q3],RL2EN,CLK8,!RL2EN);
END;

SYM GLB  B5  1  RL3_CONTROL;
EQUATIONS

RL3	=	RL3EN
	#	RL3.PIN & !RL3_TO.PIN;

RL3EN.D =	(!_B7 # WD_TO)
	#	RL3EN & !RL3_TO.PIN;

RL3_TO	=	!_RL3_4 & RL3Q5
	#	!_RL3_8 & RL3Q6
	#	!_RL3_16 & RL3Q7;

RL3EN.CLK	=	CLK8;

END;
END;

SYM GLB  B4  1  WDOG_CONTROL;
//WATCHDOG Counter control
EQUATIONS

WDOG	=	B4_NE
	#	WDOG.PIN & !WDCD;

WDCD.D =	WDOG.PIN # WD_TO.PIN # !_WDDIS;

WD_TO	=	!_WD30 & WDQ7 & WDQ6 & WDQ5 & WDQ4
	#	!_WD2M & WDQ9 & WDQ8 & WDQ7 & WDQ6
	#	!_WD8M & WDQ11 & WDQ10 & WDQ9 & WDQ8;


question: square parenthesis usually indicates a set, as in [Q3..Q0]
what is happening here?
Code: 
[WDCD].CLK	=	CLK8;

END;
END;

SYM GLB  B3  1  WD_D;
 CBU516_4 ([WDQ12..WDQ15],[WDQ0..WDQ11],CLK8,VCC,WDCD);
END;

SYM GLB  B2  1  WD_C;
 CBU516_3 ([WDQ8..WDQ11],[WDQ0..WDQ7],CLK8,VCC,WDCD);
END;

SYM GLB  B1  1  WD_B;
 CBU516_2 ([WDQ4..WDQ7],[WDQ0..WDQ3],CLK8,VCC,WDCD);
END;

SYM GLB  B0  1  WD_A;
 CBU516_1 ([WDQ0..WDQ3],CLK8,VCC,WDCD);
END;


question: in following section, what is significance of underscores?
and of the square parenthesis?

Code: 
SYM GLB  A6  1  B4 Edge Control;
//Edge pulse generation
EQUATIONS

_B4D.d	=	_B4;

_B4DD.d	=	_B4D;

B4_NE.d	=	!_B4D & !_B4DD;

[_B4D, _B4DD, B4_NE].CLK = CLK8;

END;
END;

I/O pin assignments
format SYM IOC (cpld pin name)

Code: 
SYM IOC  IO31  1  !M_RST;
XPIN IO X!M_RST LOCK 4;   
 OB21 (X!M_RST,RL3);
END;

SYM IOC  IO30  1  RL3;
XPIN IO XRL3 LOCK 3 PULLUP=OFF;   
 OB11 (XRL3,RL3);
END;

SYM IOC  IO29  1  RL2;
XPIN IO XRL2 LOCK 2 PULLUP=OFF;   
 OB11 (XRL2,RL2);
END;

SYM IOC  IO28  1  RL1;
XPIN IO XRL1 LOCK 1 PULLUP=OFF;   
 OB11 (XRL1,RL1);
END;

SYM IOC  IO27  1  WDOG;
XPIN IO XWDOG LOCK 44 PULLUP=OFF;   
 OB11 (XWDOG,WDOG);
END;

SYM IOC  Y0  1  CLK8;
XPIN CLK XCLK8 LOCK 5;  
 IB11 (CLK8,XCLK8);
END;

SYM IOC  I3  1  CLK2;
XPIN GOE XCLK2 LOCK 40;  
 IB11 (CLK2,XCLK2);
END;

SYM IOC  IO16  1  WD30;
XPIN IO X_WD30 LOCK 31;  
 IB11 (_WD30,X_WD30);
END;

SYM IOC  IO17  1  WD2M;
XPIN IO X_WD2M LOCK 32;  
 IB11 (_WD2M,X_WD2M);
END;

SYM IOC  IO18  1  WD8M;
XPIN IO X_WD8M LOCK 33;  
 IB11 (_WD8M,X_WD8M);
END;

SYM IOC  IO19  1  WDDIS;
XPIN IO X_WDDIS LOCK 34;  
 IB11 (_WDDIS,X_WDDIS);
END;

SYM IOC  IO0  1  B4;
XPIN IO X_B4 LOCK 9;  
 IB11 (_B4,X_B4);
END;

SYM IOC  IO1  1  B5;
XPIN IO X_B5 LOCK 10;  
 IB11 (_B5,X_B5);
END;

SYM IOC  IO2  1  B6;
XPIN IO X_B6 LOCK 11;  
 IB11 (_B6,X_B6);
END;

SYM IOC  IO3  1  B7;
XPIN IO X_B7 LOCK 12;  
 IB11 (_B7,X_B7);
END;

SYM IOC  IO4  1  RL1_4;
XPIN IO X_RL1_4 LOCK 13;  
 IB11 (_RL1_4,X_RL1_4);
END;

SYM IOC  IO5  1  RL1_8;
XPIN IO X_RL1_8 LOCK 14;  
 IB11 (_RL1_8,X_RL1_8);
END;

SYM IOC  IO6  1  RL1_16;
XPIN IO X_RL1_16 LOCK 15;  
 IB11 (_RL1_16,X_RL1_16);
END;

SYM IOC  IO7  1  RL2_4;
XPIN IO X_RL2_4 LOCK 16;  
 IB11 (_RL2_4,X_RL2_4);
END;

SYM IOC  IO8  1  RL2_8;
XPIN IO X_RL2_8 LOCK 19;  
 IB11 (_RL2_8,X_RL2_8);
END;

SYM IOC  IO9  1  RL2_16;
XPIN IO X_RL2_16 LOCK 20;  
 IB11 (_RL2_16,X_RL2_16);
END;

SYM IOC  IO10  1  RL3_4;
XPIN IO X_RL3_4 LOCK 21;  
 IB11 (_RL3_4,X_RL3_4);
END;

SYM IOC  IO11  1  RL3_8;
XPIN IO X_RL3_8 LOCK 22;  
 IB11 (_RL3_8,X_RL3_8);
END;

SYM IOC  IO12  1  RL3_16;
XPIN IO X_RL3_16 LOCK 23;  
 IB11 (_RL3_16,X_RL3_16);
END;
END;  //LDF DESIGNLDF
 
Last edited by a moderator:

FYI this file is probably tool generated...probably a combination of ABEL and tool specific additions. I thought I recall Lattice had a GUI for entering ABEL code, probably saved it with a bunch of extra tool generated stuff.

OPTION ISP ON;
OPTION PULLUP ON;
Click to expand...
In System Programming
Weak pullups on pins

Verifying the equations would take more time than I can spend...sorry about that.

Those statements for CBU58_1, CBU516_4, etc with the [......] stuff I'm pretty sure a just buses of signals, but I don't recall using stuff like this much when I wrote in ABEL for PLDs.

The underscores usually meant active low back in those days.

I'm pretty sure the [........].CLK is applying the same clock CLK8 to all the registers. It's just a short hand way of writing it instead of writing them all out individually.

Sorry I can't be of more help...it's been more than 25 years since I last wrote any ABEL code.
 
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