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  1. #1
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    Single nibble Binary to Hexadecimal 7 Segment decoder for making your own CPLD

    I have loads of 9572XL's and have been needing a Binary to Hexadecimal 7 Segment decoder. There used to be loads of these devices but now they are like hens teeth, I haven't yet tried this out in one of my CPLD's but the logic has been tested and it works.

    Click image for larger version. 

Name:	Binary to Hex 7 Segment decoder.jpg 
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    You set the binary values by loading them into D0 through D3.

    When enable is low only a '-' will be displayed regardless of what value is loaded when it is driven high the value then shows on the display, this is so you can have a power on state that reflects no value yet being loaded.

    Once I have transferred the logic into a CPLD, ill upload the verilog.

    I hope this helps someone as I noted a couple of questions regarding this sort of thing previously and saw PIC's mentioned, I will also work on a multi display charlie plexed version but that will be some time off.

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  2. #2
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    Re: Single nibble Binary to Hexadecimal 7 Segment decoder for making your own CPLD

    Here is a reduced logic count version for anyone who is following this.

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Name:	Binary to Hex 7 Segment decoder Reduced logic count.jpg 
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  3. #3
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    Re: Single nibble Binary to Hexadecimal 7 Segment decoder for making your own CPLD

    And I think that this - rev 4 will be the final version unless someone else can see some circuitry that is doubled up.

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Name:	Binary to Hex 7 Segment decoder Reduced logic count rev 4.jpg 
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    There may be one or possibly even two replicated circuits in there but if there are I can't see them, being able to print it out would be an advantage for doing manual gate reduction but at the moment my printer is out of commission. I'm going to see what Xilinx Vivaldo thinks of the rev 4 schematic, should be done by Wednesday if any ones actually following this.

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