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Unfamiliar VHDL | operator

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shaiko

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Hello,

What does the VHDL '|' (like bitwise or in C) operator do ?
 

Its not an operator.
It allows you to select multiple cases with case or with..select statements:

Code VHDL - [expand]
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signal a : integer;
 
....
 
case a is
  when 0 =>
  when 1 to 14 =>
  when 15 | 20 | 25 =>
  when others => 
end case;
 
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